We propose to use the Hall response of topological defects, such as merons and antimerons, spin currents in two-dimensional magnetic insulator with in-plane anisotropy for identification Berezinskii-Kosterlitz-Thouless (BKT) transition a transistorlike geometry. Our numerical results relying on combination Monte Carlo dynamics simulations show from superfluidity conventional transport, accompan...

This chapter shows a minimum-width transistor placement method which is applicable to CMOS cells in presence of non-dual P and N type transistors, whereas the cell layout synthesis methods explained in the previous chapters are only for dual cells. This chapter only targets the minimum-width transistor placement, and does not take the intra-cell routings into consideration. The proposed method ...

There are two types of field-effect transistors, the Junction Field-Effect Transistor (JFET) and the “Metal-Oxide Semiconductor” Field-Effect Transistor (MOSFET), or Insulated-Gate Field-Effect Transistor (IGFET). The principles on which these devices operate (current controlled by an electric field) are very similar — the primary difference being in the methods by which the control element is ...

A novel method for the reduction of subthreshold slope below the room-temperature Boltzmann limit of 60 mV/dec for a field-effect transistor based on negative differential capacitance is proposed. This effect uses electric field induced electrostriction of a piezoelectric gate barrier of the transistor. The mechanism amplifies the internal surface potential over the applied gate voltage. This i...

Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for evaluating the effectiveness of each of these approaches independently and in conjunction with each other. Results show the advantages of multiple supply, transistor sizing, and multiple threshold can be compounded to...

A simple method for transistor DC parameter extraction is presented, where the self-heating of the transistor is taken into account. The thermal behaviour of the transistor is modelled using a single thermal resistance, whose value is extracted simultaneously with the electrical parameters. When pulsed measurements are performed the usage of the thermal resistance, as an effective thermal resis...

In this study, the impact of negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated compared to those baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) saturation 0.5 modes. Sentaurus TCAD MATLAB were used for simulation JL-NWFET (NC-JL-NWFET...