In the deep sub-micron regime, the performance of network-on-chip (NoC) architectures is bound by the limited power and area budget. Proposed is a low-power low-area NoC architecture using a novel power-efficient control circuit that enables repeaters along the interrouter links to function as adaptive link buffers, thereby reducing the number of buffers required in the router. Simulation resul...

The security of audio as well as video data in high end communication applications like satellites and radars is an issue of concern these days. Designing a processor at the chip level for this requirement is by itself a challenge to VLSI engineers. This paper aims to design a HDL based Modified low power low area audio sub word sorter unit, which is very less complex in structure and highly ef...

this paper presents a novel fully differential (FD) ultra high common mode rejection ratio (CMRR) current operational amplifier (COA) with very low input impedance. Its FD structure that attenuates common mode signals over all stages grants ultra high CMRR and power supply rejection ratio (PSRR) that makes it suitable for mixed mode and accurate applications. Its performance is verified by HSPI...

this paper mainly focused on implementation of aes encryption and decryption standard aes-128. all the transformations of both encryption and decryption are simulated using an iterativedesign approach in order to minimize the hardware consumption. this method can make it avery low-complex architecture, especially in saving the hardware resource in implementing theaes inversesub bytes module and...

Low-power wide-area networks (LPWANs) are emerging technologies aiming at serving sporadic IoT traffic. While reliability of LPWANs in single-technology deployment has been well investigated, there is lack research on performance evaluation coexisting scenarios. To tackle this problem, we start by modeling statistics aggregated interference from asynchronous sources over shared radio resources....