In this paper, a high speed and low power 16x16 Vedic Multiplier is designed by using low power and high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the intermediate stages of the Carry Select Adder (CSA) which is known to be the fastest adder among the conventional adder structures. A Novel technique for digit multiplication namely Vedi...

Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps n any high speed ALUs that can be used varies processors and applicable for IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are fundamental building block perform arithmetic operation. In this paper, different types high-speed, 6T-XOR/XNOR-cell de...

Two new low-power, and high-performance 1bit Full Adder cells are proposed in this paper. These cells are based on low-power XOR/XNOR circuit and Majority-not gate. Majority-not gate, which produces Cout (Output Carry), is implemented with an efficient method, using input capacitors and a static CMOS inverter. This kind of implementation benefits from low power consumption, a high degree of reg...

This paper describes the impact of crosstalk noise on low power design techniques based on voltage scaling. I t is shown that this power saving strategy aggmvates the crosstalk noise problem and reduces circuit noise immunity. A new energy-eficient, noise-tolerant dynamic circuit technique is presented to address this problem. In a 0.35pm CMOS technology and at a given supply voltage, the propo...

Reversible computation is of the growing interests to power minimization having applications in low power CMOS design, quantum computing, optical information processing, DNA computing, bioinformatics and nanotechnology. This paper proposes a novel 4x4 bit reversible Multiplier circuit. It is faster and has lower hardware complexity compared to the existing designs. In addition, the proposed rev...

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based ...

In this paper the performance of 8-transistor based Full adder is analyzed, evaluated, and compared with that of three different types of Full Adders based on Complementary Pass Transistor XOR Logic gate. Simulation results using nano-scale SPICE parameters are obtained for the above mentioned FAs. It is shown that the performance of the 8-transistor based Full adder in term of power dissipatio...

In this paper we have find great applicability in RNS implementation for the Diminished-one modulo 2n+1 Adder using Circular Carry Selection (CCS) circuit. This adder presents a modulo addition of different bit values for n = 8, 12, 16, 24, 32, 48, 64. We are using the Diminished-one criteria using Circular Carry Selection (CCS) technique for the proposed modulo adder. The circuit design of pro...

1. Introduction Power has become a primary design constraint in digital integrated circuits. Most designs in sub-100nm technologies will either maximize the performance under power constraints or minimize the energy for required amount of computation. To achieve the optimality in power-performance space, integrated circuits have to be optimized at all levels of hierarchy: device, circuit, micro...