In this position paper, we discuss the interdependencies of context models and flexible design processes in the chip industry. We illustrate this by an ontology-based context model for digital design processes. Open issues concern the role of context adaptation for a case-based authoring support of the process models as well as the representation and explanation of changes of the context model.

Optimization algorithms used in binary multi-level logic synthesis, such as network simplification, logic extraction, and resubstitution, have been treated independently and did not share computational procedures. Using multi-valued logic synthesis, some common conceptual and computational cores underlying these algorithms can be identified. We present an overview of a Boolean paradigm in multi...

MVSIS is a logic synthesis system, which enhances traditional binary logic synthesis with capabilities related to multi-value logic. This manual introduces the programming environment of MVSIS 2.0 and compares it with those of SIS 1.3 and VIS 1.4. The new data structures are described and the motivation behind them is explained. The goal is to help the reader with the general understanding of l...

Syllabification information is a valuable component in speech synthesis systems. Linguistic rule-based methods have been assumed to be the best technique for determining the syllabification of unknown words. This has recently been shown to be incorrect for the English language where data-driven algorithms have been shown to outperform rule-based methods. It may be possible, however, that data-d...

This paper presents work in progress on an adaptive workflow management tool for digital design projects. The chip design follows standardized default processes which are adapted during an ongoing project by changing requirements from both design and application uncertainties. Our approach focuses on flexible monitoring and case-based authoring support of adaptive workflows in order to support ...

Logic synthesis Examples with Known Upper bound by Cong and Minkovich are circuits hard to synthesize and map to look-up tables. During experiments with the synthesis of these examples, a way to obtain reasonable results was discovered. The crucial step is to abandon the circuit structure, and to describe the circuit independently of its structure. The feasibility of taking such an approach in ...

We present new algorithms to synthesize exact universal reversible gate library for various types of gates and costs. We use the powerful algebraic software GAP for implementation and examination of our algorithms and the reversible logic synthesis problems have been reduced to group theory problems. It is shown that minimization of arbitrary cost functions of gates and orders of magnitude are ...

The inductive synthesis of recursive logic programs from incomplete information, such as input/output examples, is a challenging subfield both of ILP (Inductive Logic Programming) and of the synthesis (in general) of logic programs from formal specifications. We first overview past and present achievements, focusing on the techniques that were designed specifically for the inductive synthesis o...