This thesis describes the development and evaluation of three algorithms for the placement of parallelized applications on future many-core processors. The algorithms are able to compensate for permanent hardware faults and thereby cause a graceful degradation rather than a program crash. The fault model considers permanently failed cores, routers and processor interconnect links. The main goal...

In this work, we consider the reformulation of hierarchical (H) matrix algorithms for many-core processors with a model implementation on graphics processing units (GPUs). H matrices approximate specific dense matrices, e.g., from discretized integral equations or kernel ridge regression, leading to log-linear time complexity in dense matrix-vector products. The parallelization of H matrix oper...

With the approaching of the many-core era, it becomes more and more difficult for a single OpenMP application to efficiently utilize all the available processor cores. On the other hand, the available cores become more than necessary for some applications. We believe executing multiple OpenMP applications concurrently will be a common usage model in the future. In this model, how threads are sc...

In recent years, advancement in technology and computing led to huge amounts of data being generated. Thus, HighPerformance Computing (HPC) plays an ever growing role in processing these large datasets in a timely fashion. Our analysis consist of few important throughput computing app kernels which have high degree of parallelism and makes them excellent candidates for evaluation on high end mu...

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Examples of Highly-threaded Many-core Architectures . . . . . . . . . . . . 4 1.2 Research Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 Methodology for Performance Modeling . . . . . . . ...

With the shift from highly clocked, single thread processors to chips that have dozens or even hundreds of smaller processors, we are witnessing a fundamental change in the computing hardware we use. This paper describes an approach to use modern many-core-hardware to apply real time ray tracing to Virtual Reality environments. We show that current hardware can speed up real time ray tracing to...

The memory system of a modern embedded processor consumes a large fraction of total system energy. We explore a range of different configuration options and show that a reconfigurable design can make better use of the resources available to it than any fixed implementation, and provide large improvements in both performance and energy consumption. Reconfigurability becomes increasingly useful a...

Many-core GPUs provide high computing ability and substantial bandwidth; however, optimizing irregular applications like SpMV on GPUs becomes a difficult but meaningful task. In this paper, we propose a novel method to improve the performance of SpMV on GPUs. A new storage format called HYB-R is proposed to exploit GPU architecture more efficiently. The COO portion of the matrix is partitioned ...

Homomorphic hash functions (HHF) play a key role in securing distributed systems that use coding techniques such as erasure coding and network coding. The computational complexity of HHFs remains to be a main challenge. In this paper, we present a massively parallel solution, named Tsunami, by exploiting the widely available many-core Graphic Processing Units (GPUs). Tsunami includes the follow...

Many-core Systems-on-Chip (SoCs) are of increasing significance in the domain of high-performance embedded computing systems where high performance requirements meet stringent timing constraints. The high computing power offered by many-core SoCs, however, does not necessarily translate into high performance. On the one hand, the use of deep submicrometer process technology to fabricate SoCs im...