This paper introduces a new hybrid algorithm for locating all solutions in multimodal optimization problems. This algorithm combines an adaptive sequential niche techniquewith deterministic local optimization to detect all extrema efficiently and reliably. A genetic element of the hybrid algorithm performs W vailable online 9 March 2009

Memory built-in self-test (BIST) is a widely used technique to allow the and self-checking of embedded memories on chips after fabrication process. It can be by implementing standard testing algorithm available in EDA tool library or user-defined (UDA). This paper presents development software that automatically generates description file UDA deployed for memory BIST circuit implementation usin...

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist the memory are described, terms of definition detection requirement. Several testing algorithms that used built-in self-test (BIST) discussed, test operation sequences, ability, also ...

The purpose of this paper is to present a polynomial time algorithm which determines the lot sizes for purchase component in Material Requirement Planning (MRP) environments with deterministic time-phased demand with zero lead time. In this model, backlog is not permitted, the unit purchasing price is based on the all-units discount system and resale of the excess units is possible at the order...