نتایج جستجو برای: memory architecture
تعداد نتایج: 475651 فیلتر نتایج به سال:
A processing-in-memory architecture for exascale systems R. Nair S. F. Antao C. Bertolli P. Bose J. R. Brunheroto T. Chen C.-Y. Cher C. H. A. Costa J. Doi C. Evangelinos B. M. Fleischer T. W. Fox D. S. Gallo L. Grinberg J. A. Gunnels A. C. Jacob P. Jacob H. M. Jacobson T. Karkhanis C. Kim J. H. Moreno J. K. O’Brien M. Ohmacht Y. Park D. A. Prener B. S. Rosenburg K. D. Ryu O. Sallenave M. J. Ser...
Processor performance has been improved due to clock acceleration and ILP extraction techniques. Performance of main memory, however, has not been improved so much. The performance gap between processor and memory will be growing further in the future. This is very serious problem in high performance computing because effective performance is limited by memory ability in most cases. In order to...
Recently a great deal of attention has been paid to the design of hierarchical shared memory cluster system. Cluster computing has made hierarchical computing systems increasingly common as target environment for large-scale scientific computations. This paper proposes hierarchical shared memory cluster architecture with load balancing and fault tolerance. Hierarchies of shared memory and cache...
This paper proposes a cognitive architecture based on Kahneman’s dual process theory [1]. The long-term memory is modeled as a transparent neural network that develops autonomously by interacting with the environment. The working memory is modeled as a buffer containing nodes of the long-term memory. Computations are defined as processes in which working memory content is transformed according ...
In recent computer systems, a large portion of energy is consumed by on-chip cache accesses and data movement between cache and off-chip main memory. Reducing these memory system energy is indispensable for future microprocessors because power and thermal issues certainly become a key factor of limiting processor performance. In this paper, we discuss and evaluate how our architecture called SC...
This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum ope...
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