A development of an intelligent traffic signal control (ITSC) system needed because present traffic light controllers are based on old microcontroller such as AT89C51 which has very less internal memory and no in-built ADC. These systems have limitation because they will use the predefined program that does not have the flexibility of modification on real time application. The present traffic s...

1. Introduction Logic Built-In Self-Test (BIST) schemes based on STUMPS structure use on-chip circuitry to generate test stimuli and analyze test responses, with little or no help from an ATE. The STUMPS (Self-Test Using a MISR and Parallel Shift register sequence generator) structure applies pseudo-random patterns generated by a PRPG (Pseudo-Random Pattern Generator) to a full-scan circuit in ...

Built-in self-test (BIST) is an attractive approach to detect delay faults because of its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique that has been successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes has increased. However, an extension to delay fault test...

This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, coverage and touchdown time for...

We present the first delay-fault testing approach for Field Programmable Gate Arrays (FPGAs), applicable for on-line testing as well as for off-line manufacturing and system-level testing. Our approach is based on Built-In Self-Test (BIST), it is comprehensive, and does not require expensive external test equipment (ATE). We have successfully implemented this BIST approach for delay-fault testi...

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnost...

background and aim: today, bilingualism is a developing phenomenon which half of the world population is bilingual. auditory system is the main route to language learning, so it is expected that bilingualism has an effect on functions of the auditory system. auditory memory is one of the auditory processes which is a cornerstone of linguistic skills and learning process growth, so that, it has ...

bile duct ligation (bdl) is shown to induce cholestasis-related liver function impairments as well as consequent cognitive dysfunctions (i.e. impaired learning and memory formation). this study investigates the effects of cholestasis (14, 21 and 28 days post bile duct ligation) on spatial and non-spatial novelty detection, using a non-associative task. male mice weighing 30-35 g were used. chol...

objectives: the prospective and retrospective memory questionnaire (prmq) developed by smith (2000) and consists of a series of questions about memory weakness that can be encountered anyone in everyday life. the self-reported questionnaire has 16 items that assessing of prospective and retrospective memory problems in everyday life and the aim of the present research was to examine the investi...

This paper proposes a advance technology which is completely innovative and creative. The urge of inventing this proposal lies on the bases of the idea of making a pen drive have an extendable memory capacity with a modern and digitalized look. This device can operate without the use of a computer system or a mobile. The computerized pen drive has a display unit to display the contents of the p...