Digital mobile communication technologies, such as next generation mobile communication and mobile TV, are rapidly advancing. Hardware designs to provide baseband processing of new protocol standards are being actively attempted, because of concurrently emerging multiple standards and diverse needs on device functions, hardwareonly implementation may have reached a limit. To overcome this chall...

The many-core era is different. The nature of programmers, the nature of applications, and the nature of the computing substrate are different for multi-core chips than the traditional parallel machines that drove the parallel programming debate in the past. Specifically, while traditional parallel computers were programmed by highlyeducated scientists, multi-core chips will be programmed by ma...

Sourcery VSIPL++ for the Cell/B.E. [1][2] is an implementation of the open standard VSIPL++ signal and image-processing API [1] on the IBM Cell/B.E. multi-core processor architecture [4]. It is suitable for implementing high-performance signal-processing applications that take full advantage of the Cell/B.E. processor throughput, without sacrificing programmer productivity or application portab...

In this paper we propose a model of distributed multi-core processors with software controlled dynamic voltage scaling. We consider the problem of energy efficient task scheduling with a given deadline on this model. We consider send-receive task graphs in which the initial task sends data to multiple intermediate tasks, and the final task collects the data from these intermediate tasks with th...

The challenge of improving the performance of current processors is achieved by increasing the integration scale. This carries a growing vulnerability to transient faults, which increase their impact on multicore clusters running large scientific parallel applications. The requirement for enhancing the reliability of these systems, coupled with the high cost of rerunning the application from th...

This paper presents the concept and preliminary tests in FPGA of a specific architecture for a flexible multicore microcontroller. It is aimed to intermediate complexity embedded applications. A previous exact characterize of the microcontroller model and its target applications is a costly-time task, and it depends mostly on experience of the engineers and programmers. The proposed architectur...

We present the implementation and performance of a new gravitational N body tree-code that is specifically designed for the graphics processing unit (GPU) . All parts of the tree-code algorithm are executed on the GPU. We present algorithms for parallel construction and traversing of sparse octrees. These algorithms are implemented in CUDA and tested on NVIDIA GPUs, but they are portable to Ope...

In this paper, we introduce a model for multicore architectures, which takes into explicit consideration the cache-oriented nature of inputs and outputs in modern CPUs. In addition, we study the fundamental problem of sorting comparable items using this model. We provide algorithms that are efficient in terms of the number of parallel I/O’s. We also provide lower bounds that show that our algor...

This session deals with modeling and simulating extra-functional system properties. The first paper presents a framework to accurately model the power and timing of hardware models without requiring a full micro-architectural simulation of the hardware module to extract signal transitions. The second paper presents a method to extend Design Space Exploration (DSE) of systems with Out-of-Order e...

This deliverable reports our early energy models for data structures and algorithms based on both micro-benchmarks and concurrent algorithms. It reports the early results of Task 2.1 on investigating and modeling the trade-off between energy and performance in concurrent data structures and algorithms, which forms the basis for the whole work package 2 (WP2). The work has been conducted on the ...