 To achieve performance, Explicitly Parallel Instruction Computing (EPIC) systems take the responsibility of extracting instruction-level parallelism (ILP) from the hardware and give it to the compiler. They expose a large part of the hardware control at the conventional machine level. Dynamically Trace Scheduled VLIW (DTSVLIW) systems, on the other hand, leave the responsibility of extracting...

The origins of conventional literacy skills are evident in early childhood development. Emergent literacy skills, as measured in preschool and kindergarten, are strong predictors of later literacy achievement. Current educational research and policy (e.g., No Child Left Behind Act of 2001, PL 107-110, 115 Stat. 1425, 2001) emphasize assessment of preschool children to inform identification and ...

Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved: SIMD Within A Register (SWAR). Unlike other styles of SIMD hardware, SWAR models are tuned to be integrated within conventional microprocessors, using their existing memory reference and instruction handling mechanis...

This paper presents a new merit function for custom instruction selection phase of the design flow of application-specific instruction-set processors (ASIPs) in the presence of an area budget constraint. In contrast to nearly all of the previously proposed approaches where ratio of the ASIP speed to layout area is used as a merit function to select the candidate custom instructions (CIs), we sh...

this study investigates and compares the efficacy of differentiated instruction and traditional-based instruction on enhancing iranian students’ reading comprehension. eight elementary, intermediate, and advanced classrooms from 1 language institute were chosen, and based on their performance on the pretests were further divided into 4 control and 4 treatment groups. flexible grouping, tiered i...

Superscalar and superpipelining techniques increase the overlap between the instructions in a pipelined processor, and thus these techniques have the potential to improve processor performance by decreasing the average number of cycles between the execution of adjacent instructions. Yet, to obtain this potential performance benefit, an instruction scheduler for this high-performance processor m...

Finding an optimal assignment of program variables into registers and memory is prohibitively difficult in code generation for application specific instruction-set processors (ASIPs). This is mainly because, in order to meet stringent speed and power requirements for embedded applications, ASIPs commonly employ non-orthogonal architectures which are typically characterized by irregular data pat...