This paper presents a scalable FPGA/ASIC implementation architecture for high-speed parallel table-lookup-coding using multiported content addressable memory, aiming at facilitating effective tablelookup-coding solutions. The multi-ported CAM adopts a Flexible Multiported Content Addressable Memory (FMCAM) technology, which represents an effective parallel processing architecture and was previo...

Two innovative high-speed low power parallel 8-bit counter architectures are proposed. Then, High speed 8-bit frequency divider circuits using the proposed architectures are realized. The proposed parallel counter architectures consist of two sections – The Counting Path and the State Excitation Module. The counting path consists of three counting modules in which the first module (basic module...

An extensible machine architecture is devised to efficiently support a parallel reduction model of computation. The organisation of the machine is designed to match the behaviour of the application programs. A pilot implementation of the architecture is used to obtain an execution profile of the various applications. These profiles are used with a performance model to calculate optimal schedule...

The MULTIPLUSproject aims at the development of a modular parallel architecture suitable for the study of several aspects of parallelism in both true shared memory and virtual shared memory environments. The MULTIPLUS architecture is able to support up to 1024 Processing Elements based on SPARC microprocessors. The MULPLIX Unix-like operating system offers a suitable parallel programming enviro...

In this paper, a parallel, power-efficient and scalable word-based crypto architecture is proposed that performs the operations required for scalar point multiplication including add, multiplication and inversion operations on GF(2) operands. The proposed architecture distinguishes itself from exiting architectures, including our prior architecture, by the fact that its resource usage and power...

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible the 5th generation (5G) new radio (NR). Basing on algorithm, we propose high area-efficient encoder architecture. The proposed has advantages of and pipelined operations. Furthermore, it designed as configurable structure, fully different base graphs 5...