In this paper, we present a new efficient distributed arithmetic (NEDA) formulation of the computation of 1-D discrete wavelet transform (DWT) using 9/7 filters, and mapped that into bit parallel for high-speed and low hardware implementations, respectively. We demonstrate that NEDA is a very efficient architecture with adders as the main component and free of ROM, multiplication, and subtracti...

In high speed applications, multipliers and their associated circuits like accumulators, half adders, and full adders consume a significant portion. Therefore, it is necessary to increase their performance as well as size efficiency. In order to reduce the hardware complexity which ultimately reduces an area and power, energy efficient full adders plays crucial role in Wallace tree multiplier. ...

let $g$ be a $p$-group of nilpotency class $k$ with finite exponent $exp(g)$ and let $m=lfloorlog_pk floor$. we show that $exp(m^{(c)}(g))$ divides $exp(g)p^{m(k-1)}$, for all $cgeq1$, where $m^{(c)}(g)$ denotes the c-nilpotent multiplier of $g$. this implies that $exp( m(g))$ divides $exp(g)$, for all finite $p$-groups of class at most $p-1$. moreover, we show that our result is an improvement...

Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing technology is an advanced transmission technique for wireless communication systems. In this paper, the 64 point pipeline FFT/IFFT processor is introduced for efficient implementation of OFDM architecture. The IFFT processor is used to modulate the subcarrier in transmitter section and FFT processor demodulate the subcarr...

The 2-Lagrange multiplier method is a domain decomposition method which can be used to parallelize the solution of linear problems arising from partial differential equations. In order to scale to large numbers of subdomains and processors, domain decomposition methods require a coarse grid correction to transport low frequency information more rapidly between subdomains that are far apart. We ...

We introduce and study a Fock-space noncommutative analogue of reproducing kernel Hilbert spaces of de Branges-Rovnyak type. Results include: use of the de Branges-Rovnyak space H(KS) as the state space for the unique (up to unitary equivalence) observable, coisometric transfer-function realization of the Schur-class multiplier S, realization-theoretic characterization of inner Schur-class mult...

Montgomery multiplication in GF(2m) is defined by a(x)b(x)r 1(x) mod f(x), where the field is generated by irreducible polynomial f(x), a(x) and b(x) are two field elements in GF(2m), and r(x) is a fixed field element in GF(2m). In this paper, first we present a generalized Montgomery multiplication algorithm in GF(2m). Then by choosing r(X) according to f(x), we show that efficient architectur...

The problems with synchronous designs at higb clock frequencies have been well documented. This makes an asynchronous approach attractive for high speed technologies like GaAs. We investigate the issues involved by describing the design of a parallel multiplier that can be part of a floating point multiplier. We first present a new architecture called the partial array of array (PAA) that is mo...

FPGAs are increasingly being applied to DSP applications but are often inefficient in space and time compared with dedicated DSP chips, particularly for multiplication-based operations. To improve FPGA arithmetic performance, a flexible multiplication unit and configurable carry logic circuitry suitable for incorporation into a FPGA logic block are proposed. The multiplier unit is based on a mo...