We introduce an exactly solvable model of interacting Majorana fermions realizing Z2 topological order with a Z2 fermion parity grading and lattice symmetries permuting the three fundamental anyon types. We propose a concrete physical realization by utilizing quantum phase slips in an array of Josephson-coupled mesoscopic topological superconductors, which can be implemented in a wide range of ...

We provide a proof that a logarithmic redundancy factor is necessary for the reliable computation of the parity function by means of a network with noisy gates. This is the same as the main result in [1], except that the analysis therein seems to be not entirely correct. t Department of Computer Science, University of British Columbia, Vancouver, British Columbia V6T 1W5, Canada. Research suppo...

These are the lecture notes from 2019 Les Houches Summer School on “Quantum Information Machines”. After a brief introduction to quantum error correction and bosonic codes, we focus case of cat qubits stabilized by nonlinear multi-photon driven dissipation process. We argue that such system can be seen as self-correcting qubit where bit-flip errors robustly exponentially suppressed. Next, provi...

In this work, a high performance LDPC decoder architecture is presented. It is a partially-parallel architecture for low-complexity consideration. In order to eliminate the idling time and hardware complexity in conventional partially-parallel decoders, the decoding process, decoder architecture and memory structure are optimized. Particularly, the parity-check matrix is optimally partitioned i...

In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the IEEE 802.16e WiMAX standard. The decoder supports all the code rates and codeword lengths defined in the standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest com...

Circuit minimization is a useful procedure in the field of logic synthesis. Recently, it was proven that the minimization of (∨,∧,¬) formulae is hard for the second level of the polynomial hierarchy [BU08]. The complexity of minimizing more specialized formula models was left open, however. One model used in logic synthesis is a three-level model in which the third level is composed of parity g...

Let A = (aij)k×n be a matrix with entries in the Galois field GF (2), and let x = (x1, x2, . . . , xn) be a vector of variables assuming values in GF (2). The gate complexity of A, denoted by C(A), is the minimum number of XOR gates necessary to compute the matrix-vector product Ax. In this paper it is shown that C(Hk) = 2k+1 − 2k − 2, where Hk is the parity-check matrix of the [2k − 1, 2k − k ...

Let C be a logic circuit consisting of s gates g1, g2, . . . , gs, then the output pattern of C for an input x ∈ {0, 1} is defined to be a vector (g1(x), g2(x), . . . , gs(x)) ∈ {0, 1} of the outputs of g1, g2, . . . , gs for x. For each f : {0, 1} → {0, 1}, we define an f -circuit as a logic circuit where every gate computes f , and investigate computational complexity of the following countin...

qAC 0 2] is the class of languages computable by circuits of constant depth and quasi-polynomial (2 log O(1) n) size with unbounded fan-in AND, OR, and PARITY gates. Symmetric functions are those functions that are invariant under permutations of the input variables. Thus a symmetric function f n : f0; 1g n ! f0; 1g can also be seen as a function f n : f0; 1; ; ng ! f0; 1g. We give the followin...

We consider the problem of efficiently enumerating the satisfying assignments to AC circuits. We give a zeroerror randomized algorithm which takes an AC circuit as input and constructs a set of restrictions which partitions {0, 1} so that under each restriction the value of the circuit is constant. Let d denote the depth of the circuit and cn denote the number of gates. This algorithm runs in t...