A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed adopts fall-edge-judgment phase adjuster and three-stage digitally controlled delay line to align the system input clock 0∘ output of DLL over wide frequency range, thus solving offset caused by skew. parallel-cascade configuration solve variable alignment pro...

This paper proposes a MOSFET-based all-digital temperature sensor fabricated in standard 55-nm CMOS process. The sensing elements of the are composed ring oscillators, which convert information into frequency information. ratio’s proportional to absolute (PTAT) feature is generated by using two separate oscillators with varied sensitivity. frequency-to-digital converter (FDC) converts digital r...

In this paper, we focus on instability issues of a wide-input-range Constant ON-Time buck converter. A transconductance stage in the control path that implements ripple compensation characterizes architecture switching circuit. On whole, decision rules, heavily influence stability, govern dynamical evolution We show onset sub-harmonic oscillations and pulse-bursting caused by presence hysteresi...