<p>The voltage-controlled oscillator (VCO) is the primary device in phase-locked loop (PLL) to produce local frequency. The excessive phase noise of VCOs cause PLL performance loss. This paper proposes design and optimization low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO applications with P-channel PMOS varactors spiral inductors. At 2 V supply voltage, o...

The utility grid disturbances like dc offset and harmonic components can severely affect the estimated variables from phase-locked loop (PLL), resulting in poor performance of system relying on it. Therefore, there is an emerging need for well-designed PLL algorithms ensuring robust response against different operating conditions. This paper proposes a simple single-phase algorithm with inheren...

A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a resul...

In the transient process of grid-connected converter (GCC), existing research mainly focuses on impact control loops. Little attention is paid to stability issues driven by imbalance between input power and output GCC. This paper shows that will still exist even if ignoring dynamics phase-locked loop (PLL) current loop. this paper, models AC grid GCC are built under assumption PLL ignored. Then...

Title of dissertation: LOW PHASE NOISE CMOS PLL FREQUENCY SYNTHESIZER DESIGN AND ANALYSIS Xinhua He, Doctor of Philosophy, 2007 Dissertation directed by: Professor Robert Newcomb Department of Electrical and Computer Engineering The phase-locked loop (PLL) frequency synthesizer is a critical device of wireless transceivers. It works as a local oscillator (LO) for frequency translation and chann...

This article proposes a fast and robust technique for instantaneous phase angle estimation of three-phase voltage systems under unbalanced distorted conditions. It mainly relies on the Clarke transformation, Teager energy operator, delayed signal cancellation (DSC) approach. Unlike an adaptive DSC-based synchronous-reference frame phase-locked loop (PLL), proposed avoids interdependent loops, t...

In this paper, an adaptive version of the impedance-conditioned phase-locked loop (IC-PLL), namely IC-PLL (AIC-PLL), is proposed. The has recently been proposed to address issue synchronisation with a weak AC grid by supplementing conventional synchronous reference frame (SRF-PLL) additional virtual impedance term. resulting aims synchronise converter remote and stronger point in grid, hence in...

This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-μm Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5 ps, respectively. The measured tuning range, from 4.6 to 5.0 GHz, is narrower than the expected one, from 3.8 to 5.0 GHz. The narrow tuning range issue has b...

To acquire images of dynamic scenes from multiple points of view simultaneously, the acquisition time of vision sensors should be synchronized. This paper describes an illumination-based synchronization method derived from the phase-locked loop (PLL) algorithm. Incident light to a vision sensor from an intensity-modulated illumination source serves as the reference signal for synchronization. A...

A 4 GHz PLL (phase-locked loop)-type frequency synthesizer has been implemented in the standard 0.18μm mixed-signal and RF 1P6M CMOS technology. It integrates a VCO, a dual-modulus prescaler, PFD, a charge pump, a control logic, various digital counters and digital registers onto a single chip. With the help of the linear model of the loop, the design and optimization of the loop parameters are...