The scheduling of loops for architectures which support instruction level parallelism is an important area of research. Many polynomial time, heuristic algorithms for software pipelining have been proposed for this NP-complete problem. In this research, genetic algorithms and simulated annealing are used to test the feasibility of applying artiicial intelligence techniques to the problem of sof...

This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13μm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18μm CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can re...

Many high level synthesis systems produce designs without any consideration for the underlying architecture. In such systems, tradeo s between area and delay can only be achieved by changing the synthesis constraints (e.g., number of functional units). These systems do not exploit the wider range of tradeo s that can be achieved by modifying the underlying architecture. In this report we derive...

Today Multimedia extensions are prevalent in embedded systems and in general-purpose designs. Short-vector instructions are common in these extensions. This paper presents some approaches for compilation of these instructions. These approaches d iffer in their work. Vectorization purely depends on the architecture and the software pipelining is compiler based technique which exploits ILP. Selec...

In this paper a novel technique for resource-constrained loop pipelining is presented. RCLP is based on several dependence graph operations: loop unrolling, operation retiming, resource-constrained scheduling, and span reduction. All these operations are focused to nd a minimum length schedule able to be executed with a limited number of resources and thus maximizing resource utilization. Exper...

This paper addresses the problem of parallelizing loops with conditional branches in the context of software pipelining. A new formal approach to this problem is proposed in the form of Predicated Software Pipelining (PSP) model. The PSP model represents execution of a loop with conditional branches as transitions of a finite state machine. Each node of the state machine is composed of operatio...

QR decomposition based multi-channel least square lattice (QRDMLSL) algorithm possesses good numerical property and regularity which are attractive for VLSI implementation. But due to the presence of local recursive loop in its implementation, the algorithm’s speed is limited to the computation time of each computation cell. In this paper, a novel approach for pipelining QRDMLSL adaptive filter...

This paper proposes the Pipelined SHA-3 BLAKE algorithm, running on an FPGA with the intention of developing the optimization in FPGA for BLAKE algorithm. Secured hash algorithm-3(SHA-3) BLAKE algorithm is a family of cryptographic hash function published by the National Institute of Standards and Technology (NIST). To implement BLAKE algorithm we have utilized VHDL, where we introduce the pipe...