نتایج جستجو برای: placer

تعداد نتایج: 652  

2006
Tung-Chieh Chen Zhe-Wei Jiang Tien-Chang Hsu Hsin-Chen Chen Yao-Wen Chang

In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor et al. [20] and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique...

Journal: :Technique et Science Informatiques 2002
Martin Quinson

RÉSUMÉ. Cet article présente un outil de prédiction dynamique de performances dans un environnement de metacomputing de type Client-Agent-Serveurs. Dans ce modèle, les différentes routines composant un programme peuvent être délocalisées sur des serveurs distants. Afin d’en faciliter le placement, la bibliothèque FAST (Fast Agent’s System Timer) permet aux applications appelantes d’obtenir des ...

2009
Alejandro LÓPEZ BEZANILLA

pour obtenir le grade de DOCTEUR de l'UNIVERSITÉ JOSEPH FOURIER (Arrêté ministériel du  Mars ) Etude à partir des premiers principes de l'effet de la fonctionnalisation sur le transport de charge dans les systèmes à base de carbone à l'échelle mésoscopique. Cette thèse a été composée en grande partie grâce aux logiciels T E X Louvain-la-Neuve, quienes nos han mostrado el placer de trabaja...

Journal: :Microelectronics Journal 2013
Vincent Kerzerho Serge Bernard Florence Azaïs Mariane Comte Olivier Potin Chuan Shan G. Bontorin Michel Renovell

The histogram-based technique is commonly used for testing of Analog-to-Digital Converters (ADC). One of the parameters measured thanks to this technique is the Integral Non Linearity (INL). INL is also used as an initial data related to the ADC performances for the computation of a correction table in case of a LUT-based correction technique. In this context of embedded INL measurement and emb...

Journal: :Journal of Circuits, Systems, and Computers 2005
Jing Ma Peter M. Athanas Xinming Huang

This paper presents an FPGA design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as the gate counts increase to multi-millions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, are investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the chan...

Journal: :Cahiers du Genre 2021

Cet article examine deux idéologies linguistiques qui semblent agir comme un frein à l’adoption du langage non sexiste en France – d’une part l’idéologie langue standard et de l’autre la ciment nation. Nous employons les techniques linguistique corpus l’analyse critique discours (CDA) pour analyser d’articles presse écrite française britannique. Cette approche comparative nous permet placer le ...

2010
Aaquil Bunglowala Brijmohan Singhi Ajay Verma

Focus in the present rests on optimization of multi-objective standard cell placement for maximizing the speed and minimizing power and interconnect wire-length with cell-width as a constraint. It incorporates fuzzy cost function rules for designing of multi-objectives to integrate the cost of above defined objectives. A significant improvement is reported when the iterative-constructive standa...

2003
Christoph Steiger Herbert Walder Marco Platzner Lothar Thiele

This paper deals with online scheduling of tasks to partially reconfigurable devices. Such devices are able to execute several tasks in parallel. All tasks share the reconfigurable surface as a single resource which leads to highly dynamic allocation situations. To manage such devices at runtime, we propose a reconfigurable operating system that splits into three main modules: scheduler, placer...

1999
A. E. Caldwell A. B. Kahng

We develop new optimal partitioning and placement codes for end-case processing in top-down standard-cell placement. Such codes are based on either enumeration or branch-and-bound, and are invoked for instances below prescribed size thresholds (e.g., < 30 cells for partitioning, or < 10 cells for placement). Our optimal partitioners handle tight balance constraints and uneven cell sizes transpa...

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