In this paper, we propose a pipeline scheme for efficient realization of a complex multiplier using distributed arithmetic. The pipelined multiplier consists of one conventional multiplier that is multiplexed and some small additional circuitry on the boundary. The proposed scheme reduces the chip area as well as the interconnections by nearly half compared to a conventional complex multiplier....

Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the Wallace tree structure with pipelining. A fast carry select adder is used for the final two-operand adder. It is shown that the time delay for the entire multiplier is O(log(n)). The design is particularly carried out for a 32-bit multiplier with two sections of pipelining, to bala...

We present a new low-complexity bit-parallel canonical basis multiplier for the field GF(2 m ) generated by an all-onepolynomial. The proposed canonical basis multiplier requires m 2 1 XOR gates and m 2 AND gates. We also extend this canonical basis multiplier to obtain a new bit-parallel normal basis multiplier.

In the recent year growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. In this paper a low power bypassing -based multiplier design is present, in which reduction in power...

Multipliers play a vital role in many cryptographic applications like elliptic curve cryptography, RSA and other algorithms. The direct truncation of least significant part of the product leads to large error in the resultant product when fixed width output is the requirement. This paper proposes a truncation error minimizing logic which greatly reduces truncation error. Truncation error minimi...

This study presents a novel sequential Type-I optimal normal basis multiplier in GF(2) with a regular structure. The proposed multiplier has a slightly higher space complexity than the Reyhani-Masoleh-Hasan’s (RMH) multiplier, but is 27% faster than the RMH multiplier. Furthermore, the proposed multiplier is highly regular, modular, expandable and well-suited to VLSI implementation. A new norma...

A simple and efficient modified harmonic-balance technique is presented. This new algorithm is suitable for the large-signal time-dependent analysis of nonlinear millimeter wave circuits. The accurate design and successful implementation of very high frequency nonlinear circuits requires both a detailed understanding of the physical operation of the active devices and of how these nonlinear dev...

This paper presents a self-adaptive differential evolution with augmented Lagrange multiplier method (SADE_ALM) for solving optimal power flow (OPF) problems with non-smooth generator fuel cost curves. The SADE_ALM is a modified version of conventional differential evolution (DE) by integrating mutation factor (F ) and crossover constant (CR ) as additional control variables. An augmented Lagra...

Instead of writing the Galerkin approximation as seeking the stationary point of some functional over a finite-dimensional subspace of the original function space, we write it as the initial, infinite-dimensional variational problem with an explicit constraint that models the fact that we are actually searching in a subspace. By formulating this as a constrained variational problem using a Lagr...