This paper reports three design improvements for CMOS latches hardened against single event upset (SEU) based on three memory cells appeared in recent years. The improvement drastically reduces static power dissipation, reduces the number of transistors required in the VLSI, especially when they are used in the Gate Array. The original cells and the new improved latches are compared. It is show...

Organizational techniques for reducing energy dissipation in on–chip processor caches as well as off–chip caches have been observed to provide substantial energy savings in a technology independent manner. We propose and evaluate the use of block buffering using multiple block buffers, subbanking and bit line isolation to reduce the power dissipation within on–chip caches for superscalar CPUs. ...

The power dissipation of an analog-to-digital converter (ADC) is a function of many variables, such as sampling rate (f S), resolution, architecture, process, voltage supply and technology. This chapter will attempt to establish the power dependence on sampling rate and resolution as its primary goal. To make this tenable, the scope of this task will be narrowed in the following two ways: 1. Ar...

Modern microprocessors employ one or two levels of on–chip caches that are implemented using static RAM and take up a large portion of the Silicon real estate, consuming a significant amount of power. We present detailed analytical models for estimating the energy dissipated in conventionally–organized caches as well as caches that are organized to have reduced energy dissipations. We also vali...

In this paper we address the problem of reducing the power dissipated by synchronous sequential circuits. We target the reduction of the average switching activity of the input and output state variables by minimizing the number of bit changes during state transitions. Using a probabilistic description of the nite state machines, we propose a state assignment algorithm that minimizes the Boolea...

Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be signi cantly reduced by a technique known as truncated multiplication. With this technique, the least ...

This article deals with a possibility of how to determine a power dissipation in a rotating machine. It divides losses in three parts according to their origin – losses arising around the rotating disc, in bearings, and by a friction of a shaft surface due to viscosity. A precise determination of the power dissipation is important when evaluating the efficiency of the whole device. The procedur...

This paper explores the tradeoffs that are involved in the design of SRAM. The major components of an SRAM such as the row decoders, the memory cells and the sense amplifiers have been studied in detail. The circuit techniques used to reduce the power dissipation and delay of these components has been explored and the tradeoffs have been explained. The key to low power operation in the SRAM dat...

We employ the formalism of information theory, and investigate the performance, as measured in bitenergy, of continuous/discrete-value and continuous/discrete-time signal representations as realized in electrical circuits (communication channels). We derive the signal-to-noise ratio, average power dissipation, Shannon channel capacity and bit-energy. Bit-energy, in Joules per bit, is a reasonab...

Most of the encoding methods proposed in recent years have dealt with only RC modeled VLSI interconnects. For deep submicron technologies (DSM), on-chip inductive effects have increased due to faster clock speeds, smaller signal rise times and longer length of on-chip interconnects. All these issues raise the concern for crosstalk, propagation delay and power dissipation of overall. Therefore, ...