According to research in mother tongue (L1) reading skills, successive processing the PASS Theory of Intelligence process affects reading skills through the sequential analysis and blending of phonemes and syllables. The present paper examines whether this cognitive process predicts also reading skills in English as a foreign language (EFL). A group of 81 pupils that had finished their first ye...

The main aim of this short paper is to investigate multiple-instruction-issue in a high-performance superscalar architecture, illustrating the optimum values for some processing parameters, as well as some advanced techniques for improving processor performance, such as dependence collapsing and instruction bypassing. Our analysis is based on a trace driven simulation method. The simulation res...

Analog Devices’ Blackfin processors implement a very flexible instruction set architecture geared for both control and signal processing applications. With dual MACs, a Memory Management Unit (MMU), and a control friendly instruction set, this is truly a flexible microprocessor. In particular, the inclusion of an MMU in a low cost, high performance processor with automotive peripherals has lead...

Programmable vertex processing unit increases the programmability and enables customizations of transformation and lighting in the graphics pipeline. Furthermore, it offers various effects such as procedural vertex animation and deformation, which were impossible to handle in fixed vertex processing. Since it is hard to find a programmable graphics hardware for the embedded systems such as mobi...

The centerpiece of this thesis is a new processing paradigm for exploiting instruction level parallelism. This paradigm, called the multiscalar paradigm, splits the program into many smaller tasks, and exploits fine-grain parallelism by executing multiple, possibly (control and/or data) dependent tasks in parallel using multiple processing elements. Splitting the instruction stream at staticall...

The goal of the present study was to investigate the costs and benefits of different degrees of strategic parallel processing between two tasks. In a series of experiments with the dual-task flanker paradigm, participants were either instructed to process the tasks serially or in parallel, or--in a control condition--they received no specific instruction. Results showed that the participants we...

Although many studies demonstrate large learning gains when instruction includes diagrams, diagrams do not always lead to improved outcomes. How can instructional designers know whether a given diagram will enhance learning? We have developed a framework of three factors that influence the effectiveness of a diagram in a particular learning situation: the learning objective, the design of the v...

We propose a superscalar coprocessor for high-speed curvebased cryptography. It accelerates scalar multiplication by exploiting instruction-level parallelism (ILP) dynamically and processing multiple instructions in parallel. The system-level architecture is designed so that the coprocessor can fully utilize the superscalar feature. The implementation results show that scalar multiplication of ...

This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been ext...

This paper discusses user study outcomes with teachers who used Language Muse SM a webbased teacher professional development (TPD) application designed to enhance teachers’ linguistic awareness, and support teachers in the development of language-based instructional scaffolding (support) for their English language learners (ELL). System development was grounded in literature that supports the n...