A synchronizer is a compiler that transforms a program designed to run in a synchronous network into a program that runs in an asynchronous network. The behavior of a simple synchronizer, which also represents a basic mechanism for distributed computing and for the analysis of marked graphs, was studied in ER1] and ER2] under the assumption that message transmission delays and processing times ...

Anewsoftware-baseddtestvectorcompressionn technique is proposedd for usingg ann embeddedd processor too test the other components of aa system-on-a-chipp (SOC). The tester transfers compressedd test dataa too the processor's on-chipp memory, andd the processor executes aa small program whichh decompresses the dataa andd applies it too the scann chains of eachh core-under-test. The proposedd dec...

We survey the work done so far in the FLaSH project (Functional Languages for Synthesising Hardware) in which the core ideas are (i) using a functional language SAFL to describe hardware computation; (ii) transforming SAFL programs using various meaning-preserving transformations to choose the area-time position (e.g. by resource duplication/sharing, specialisation, pipelining); and (iii) compi...

Recent advances in network technology promise to make gigabit-per-second bandwidth between remote hosts a reality in the near future. This increase in bandwidth paves the way for increased exploitation of distributed computing resources. Coupled with advances in distributed memory parallel compiler technology, there is strong reason to believe that wide-area distributed parallel processing will...

Reconfigurable computing systems have shown the potential to surpass conventional processor architectures in performance for a growing range of applications. That performance, however, must be attained without significantly changing the design effort on the programmer’s part, and without drastically increasing compilation time. In this paper, we present our compiler framework for mapping comput...

With the advance of semiconductor technology, chip multiprocessor architectures, or multi core processor architectures have attracted much attention to achieve low power consumption, high effective performance, good cost performance and short hardware/software development period. To this end, parallelizing compilers for chip multiprocessors are expected that allow us to parallelize program effe...

A new model for dynamic current analysis and simulation is presented for power and energy analysis of a complex VLIW DSP processor core, targeting secure wireless communications. Unlike other research, an instruction level RC based model, whose input parameters can be extracted from the DSP core's assembly level program, is introduced for power simulation. Experimental results utilizing several...

The increasing size and speed of modern FPGAs allow complex computations, on the order of an average sized program, to be performed in a small collection of processing elements. It is well documented that the execution of large sections of a program within the \virtual hardware" o ered by an attached FPGA processor can provide substantial speedup over the ordinary execution within a sequential,...

A model of a multiprocessing, multiprogramming computer system with serially reusable programs was developed to study the effect of serial programs on system performance. Two strategies for implementing serially reusable programs were investigated, a wait strategy in which the processor waits until the serial program is available, and a switch strategy, in which the processor is freed to do oth...

cache, a high-speed buffer establishing a storage hierarchy in the Model 85, is discussed in depth in this part, since it represents the basic organizational departure from other SYSTEM/~BO computers. Discussed are organization and operation of the cache, including the mechanisms used to locate and retrieve data needed by the processor. The internal performance studies that led to use of the ca...