Multireader shared registers are basic objects used as communication medium in asynchronous concurrent computation. We propose a scheme to obtain several wait-free constructions of bounded 1-writer multireader registers from atomic 1-writer 1-reader registers, that is easy to prove correct. Our main construction is the first one that is optimal with respect to the worstcase local use of control...

We present explicit wavefunctions for quasi-hole excitations over a variety of nonabelian quantum Hall states: the Read-Rezayi states with k ≥ 3 clustering properties and a paired spin-singlet quantum Hall state. Quasi-holes over these states constitute a topological quantum register, which can be addressed by braiding quasi-holes. We obtain the braid properties by direct inspection of the quas...

Sequential programs and algorithms are usually specified by means of preconditions and postconditions. This is not possible for concurrent and reactive programs, since their behaviour during execution is more interesting than their final states, even when termination is desirable. There are two schools in the way behaviours of concurrent and reactive programs are described. In the process algeb...

The increasing gap between CPU and memory performance forces us to reevaluate design choices made in the past to optimize the CPU-memory interface. Ideally, all CPU operand traffic would remain on-chip. It is obviously not feasible to have the number of registers be on the order of main memory size and it is not clear that increasing L1 cache sizes has significant benefit.[10] Current instructi...

Existing n-process implementations of atomic snapshots from registers use large registers. We consider the problem of implementing an m-component snapshot from small, Θ(log n)-bit registers. A natural solution is to consider simulating the large registers. Doing so straightforwardly can significantly increase the step complexity. We introduce the notion of an interruptible read and show how it ...

Let x be an m-sequence, a maximal length sequence produced by a linear feedback shift register. We show that the nondeterministic automatic complexity AN (x) is close to maximal: n/2 − AN (x) = O(log 2 n), whereas Hyde has shown AN (y) ≤ n/2 + 1 for all sequences y.

We consider the problem of building a wait-free and linearizable counter using shared registers. The counter supports a read operation, which returns the value of the counter, and an increment operation, which increments the value of the counter and returns nothing. The shared registers support read, write and compare-andswap instructions. We show that given n processes andO(n) shared registers...