In classical switching theory it is usually assumed that asynchronous sequential circuits are operated in the fundamental mode. In this mode, a circuit is started in a stable state; then the inputs are changed to cause a transition to another stable state. The inputs are not allowed to change again until the entire circuit has stabilized. In contrast to this, delay-insensitive circuits -the cor...

This short paper describes a well-known and a non-standard technique for proving properties about sequential circuits. The techniques are based on transforming the circuit to an abstract state machine, and performing several ways of induction on these state machines. We conclude with an insightful correspondence between the two techniques. The proposed methods have been implemented in an experi...

A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow e cient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be speci ed up-fro...

Most digital systems textbooks treat the topic of converting one flip flop to another by simply giving the student certain simple conversion circuits, such as the use of an inverter between the R and S inputs of an RS flip flop to form a D flip flop, or tying together the inputs of a JK flip flop to make a T flip flop. However, a more general, but very simple, methodology for flip flop conversi...

) Abstract— Static timing analysis is instrumental in efficiently verifying a design’s temporal behavior to ensure correct functionality at the required frequency. This paper addresses static timing analysis in the presence of cross talk for circuits containing levelsensitive latches, typical in high-performance designs. The paper focuses on two problems. First, coupling in a sequential circuit...

We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have been broken by using scan flip-flops (FF’s) and the control and data path parts are individually 100%testable, the composite circuit may not be easily testable by gatelevel sequential automatic test pattern generation (A...

The Bose, Chaudhuri and Hocquenghem (BCH) codes form a large class of powerful random-error correcting cyclic codes. However, the implementation of its decoder requires high-complexity computation resources with a huge number of sequential circuits. This paper presents a low-complexity register transfer level (RTL) circuit design of a BCH decoder. In accordance with the table relationship betwe...

We present a new approach to built-in self-test of sequential circuits using precomputed test sets. Our approach is especially suited to circuits containing a large number of ipops but few primary inputs. Such circuits are often encountered as embedded cores and lters for digital signal processing, and are inherently di cult to test. We show that statistical encoding of test sets can be combine...

In this paper we present two techniques for improving min-area retiming that combine the actual register minimization with combinational optimization. First, we discuss an on-the-fly retiming approach based on a sequential AND/INVERTER/REGISTER graph. With this method the circuit structure is sequentially compacted using a combination of register “dragging” and AND vertex hashing. Second, we pr...