Earlier in microcontroller based approach, every LCD display was associated with a static input. This input was static and cannot be changed by user easily as and when needed. Thus restricting the flexibility to user can have in updating the data. In this paper, we propose to design a prototype where we interface LCD display through FPGA board so as to provide flexibility of data which is being...

Better Than SCSI?1 Sangyup Shim, Taisheng Chang, Yuewei Wang, Jenwei Hsieh and David H.C. Du Distributed Multimedia Research Center & Computer Science Department, University of Minnesota Minneapolis, MN 55455 fshim, tchang, ywang, hsieh, [email protected] Abstract The existing SCSI parallel bus has been widely used in supporting multimedia applications. However, it may not fully utilize the aggreg...

Maxim has developed a family of serializer and deserializer products for high-speed, serial data interconnection in video display and digital image sensing. Today's designers are very interested in the performance measurement and margin of a serial data link established by a serializer and deserializer (SerDes) chipset. This application note presents an experimental approach first to measure th...

Abstract: The results concerning the integration of a set of power management strategies and serial communications for the efficient coordination of the power converters composing an experimental DC microgrid is presented. The DC microgrid operates in grid connected mode by means of an interlinking converter. The overall control is carried out by means of a centralized microgrid controller impl...

The capacity to remember sequences is critical to many behaviors, such as navigation and communication. Adult humans readily recall the serial order of auditory items, and this ability is commonly understood to support, in part, the speech processing for language comprehension. Theories of short-term serial recall posit either use of absolute (hierarchically structured) or relative (associative...

This paper describes the use of digit-serial arithmetic for compact and eecient implementations of real-time DSP applications on eld programmable gate arrays (FPGAs). As an example, the implementation of a digit-serial 5-tap FIR lter on a Xilinx XC4010 FPGA is considered. An analysis of the performance comparison of several FIR lters is described. The results show that digit-serial designs with...

In this paper, a set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and anti-symmetrical particular cases are also covered. All circuits have been implemented using an EPF10K50 Altera FPGA. Main results show that the canonical form presents the less occupation and the higher throug...

The bandwidth demands of modern computing systems have been continually increasing and the recent focus on parallel processing will only increase the demands placed on data communication circuits. As data rates enter the multi-Gb/s range, serial data communication architectures become attractive as compared to parallel architectures. Serial architectures have long been used in fibre optic syste...

A method to achieve maximally fast (rate-optimal) recursive filters implemented using distributed arithmetic is presented. The filters will have the same upper bound on the sample frequency as if they were implemented using bit-serial multipliers and adders. Maximally fast implementation is important for high-speed recursive filters, but also as any excess speed can be traded for low power cons...

Spread-spectrum systems with large transmission bandwidth present significant challenges from the standpoint of achieving acquisition before the communication commences. This tutorial summarizes our recent results on acquisition system that exploits multipath to aid the synchronization. In particular, we consider the serial-search strategy and the optimal search procedure to examine the uncerta...