A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with sample-and-hold (S/H) sharing technique and gain-boosted voltage-to-time (VTC) is presented for high-speed wireline communication systems. By one S/H between coarse fine stages in the ADC, input bandwidth as well area power efficiency can be improved without gain error ADCs. Thanks...

Fig. 1 N-path Time-interleaved ADC • In this paper, we propose a new calibration scheme suitable forimproving the fidelity of data-conversion in an array of ADCs, which is otherwise degraded largely due to mismatches in the non-ideaI behaviours among the individuaI ADCs in the array. This work will focus on correcting the ill-effects suffered by the array of ADCs due to mismatches in gain and o...

We demonstrate an integrated programmable photonic filter structure capable of producing bandpass filters with both tunable passband bandwidth and center frequency. Such filters could provide dynamic pre-filtering of very wide bandwidth analogmicrowave signals, essential to the next generation RF-front ends. The photonic filter is constructed from an array of uncoupled identical filter stages, ...

This paper introduces a new high-performance successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-speed and low-power wireless local area network (WLAN) applications using SMIC 55 nm 1p8m CMOS process. The design employs several innovative techniques, including an improved bootstrap switch with high linearity, 4-reference voltage method to minimize capacit...

In this paper, two techniques for implementing a lowpower pipelined analog-to-digital converter (ADC) are proposed. First, the time-interleaved correlated double sampling (CDS) technique is proposed to compensate the finite gain error of operational amplifiers in switchedcapacitor circuits without a half-rate front-end sample-and-hold amplifier (SHA). Therefore, low-gain amplifiers and the SHA-...

The integral nonlinearity (INL) is used for the post-correction of analog-digital converters (ADCs). An inputfrequency-dependent INL-model is developed for the postcorrection. The model consists of a static term that is dependent on the ADC output code and a dynamic term that has an additional dependence on the input frequency. The concept of ADC digital output post-correction by INL is first i...

در این مقاله، یک مبدل آنالوگ به دیجیتال لوله ای مبتنی بر مقایسه گر ولتاژ پایین طراحی شده است. حذف تقویت کننده و جایگزین کردن آن به وسیله یک مقایسه گر و منبع جریان تأثیر زیادی در کاهش توان مصرفی و پیچیدگی طراحی داشته است. برای طبقه اول از یک دو برابرکننده بهره خازنی به عنوان mdac استفاده شده است تا دقت لازم را برای ولتاژ خروجی طبقه اول فراهم آورد. به دلیل اثر بارگذاری طبقه دوم بر روی طبقه اول از...

This paper proposes a foreground digital calibration algorithm that estimates and corrects the offset, gain, time-skew mismatches for time-interleaved analog-to-digital converters (TIADCs) furthermore our is designed to correct harmonic distortion introduced by presence of nonlinear front-end. We propose novel simplified non-linear model in place more complex conventional Volterra series based ...

This paper describes an incremental converter based on a second order RD modulator. The scheme uses a 3-bit DAC with inherent linearity, an optimal reset of integrators, and gives rise to an effective offset cancellation with a novel technique based on single or double chopping. The circuit, fabricated in a mixed 0.18-0.6 lm CMOS technology, obtains 1.5-lV residual offset with 2VPP fully differ...