This article is present the effected oxide capacitor in CMOS structure of integrated circuit level 5 micrometer technology. It has designed and basic structure of MOS diode. It establish with aluminum metallization layer by sputtering method, oxide insulator layer mode from silicon dioxide, n and p semiconductor layer, it has high capacitance concentrate. From the MOS diode structure silicon di...

This paper provides the extracted values of the parameters affecting the threshold voltage model of SOI MOSFET. The parameter extraction is done for BSIMSOI4.3 MOSFET model. The proposed procedure is designed to give the results based on the device characteristics data. Simulations are performed using the extracted parameters and finally it is compared for extracted parameters and generic devic...

The objective of this research was to design a 0-5 GHz RF SOI switch, with 0.18um power Jazz SOI technology by using Cadence software, for health care applications. This paper introduces the design of a RF switch implemented in shunt-series topology. An insertion loss of 0.906 dB and an isolation of 30.95 dB were obtained at 5 GHz. The switch also achieved a third order distortion of 53.05 dBm ...

We investigated the source-to-drain capacitance (Csd) due to DIBL effect of silicon nanowire (SNW) MOSFETs. Short-channel SNW devices operating at high drain voltages have the positive value of Csd by DIBL effect. On the other hand, junctionless SNW MOSFETs without source/drain (S/D) PN junctions have negative or zero values by small DIBL effect. By considering the additional source-todrain cap...

We present a lateral trench gate SOI-LDMOSFET that uses narrow trenches as channels. The lateral trench gate, which allows the channel current to flow laterally on the trench side walls, decreases its on-resistance because it increases the current spreading area of the device. The specific on-resistance ðRspÞ strongly depends on the trench depth, which affects the channel area on the side wall ...

Trends in modeling and measurements of the Soft Error Rate (SER) critical charge (Qcrit) for recent generation CMOS SOI devices are reviewed. Modeling and measurements as a function of voltage on 65, 45, 32 and 22 nm planar, SOI devices will be presented. The modeling techniques used will be reviewed and, where possible, compared to experimental measurements. Finally modeling of new device stru...

The ability of the atomic force microscope ~AFM! to realize lithography patterns on silicon surfaces is widely known and leads to the formation of silicon nanostructures after an etching step. In this article, we aim at improving the fabrication process to yield silicon nanowires with minimum lateral dimensions for the realization of Coulomb blockade based devices. First, we focus on the AFM li...

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For SOI nMOSFET, the impact of high tensile stress contact etch stop layer (CESL) on device performance and reliability was investigated. In this work, device driving capability can be enhanced with thicker CESL, larger LOD and narrower gate width. With electrical and body potential inspection, serious device’s degradation happened on SOI-MOSFET with narrow gate device because of STI-induced ed...