Testing of a deeply embedded mixed-signal core in a System-on-Chip (SoC) is a challenging issue due to the communication bottleneck in accessing the core from external automatic test equipment. Consequently, in many cases the preferred approach is built-in self-test (BIST), where the major part of test activity is performed within the unit-under-test and only final results are communicated to t...

Abstract A histogram-based built-in self-test (BIST) approach for deriving main characteristic parameters of an analog to digital converter (ADC) such as offset, gain and non-linearities is proposed. The BIST uses a ramp signal as an input signal and two counters as a response analyzer to calculate the derived static parameters. Experimental results show that the proposed method makes the hardw...

The paper presents a design method for Built-In Self Test (BIST) that uses a cellular automaton (CA) for test pattern generation. We have extensively studied the quality of generated patterns and we have found several interesting properties of them. The proposed CA can generate weighted random patterns which can be used instead of linear feedback shift register (LFSR) sequences, the fault cover...

This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate efficient patterns to be used during BIST test pattern generation. The main idea is that test patterns detecting random pattern resistant faults are not embedded in a pseudo–random sequence as in existing techniques, but rat...

a-chip (SoC) architectures, demands for short time to market and rich functionality have driven design houses to adopt a new core-based SoC design flow. A core-based SoC incorporates multiple complex, heterogeneous components on a single piece of silicon; these can include digital, analog, mixed-signal, RF, micromechanical, and other kinds of systems. This blurring of the boundaries between dif...

The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that the user can be assured that their system function is downloaded to a fault-free device. In this paper, we present case studies of developing BIST configurations for some of the less thought of, though equally importa...

Power consumption for test vectors is a major problem in SOC testing using BIST. A new low power testing methodology to reduce the peak power and average power associated with scan-based designs in the deterministic BIST is proposed. This new method utilizes an auxiliary LFSR to reduce the amount of the switching activity in the deterministic BIST. Excessive transition detector (ETD) monitors t...

A Built-In Self-Test (BIST) approach is described which is designed to test the analog portion of mixed-signal integrated circuits and systems. The BIST circuitry is located in the digital portion of the mixed-signal circuitry to minimize area overhead and effects on the analog portion of the mixed-signal system. The approach was evaluated using benchmark circuits for analog testing and found t...

This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM thirdgeneration embedded dynamic random-access memory (DRAM) for the IBM Blue Logic 0.11m application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamenta...

Dependability of computer architectures has become one of the most important engineering concerns. One of the possibilities to increase the dependability is to develop architectures with dedicated self-test capabilities which allow achieving high quality of testing in terms of fault coverage. We propose a new methodology for Built-in Self-Test (BIST), which combines the inherent functionality o...