This thesis presents the design and testing of asynchronous communication mechanism (ACM) circuits, and the development of an asynchronous circuit synthesis method which not only supports the ACM work but also has much wider application potential. ACMs are a unique approach to data transmission between subsystems not synchronized with one another. The successful systematic implementation of ACM...

A rtificial intelligence (Al) has long been the topic of university research. However, only recently has this work begun providing usable Al system development tools allowing applications of Al in other research areas. This growing availability has fostered a recent trend toward applying Al techniques to improve CAD tools used to design and test integrated circuits. Both industry and universiti...

Test suites for embedded systems are typically created from scratch using different, often inadequate methods. In consequence, industry branches dealing with software-intensive embedded systems have to cope with quality problems, even though test processes are particularly time-consuming and costly. Based on an evolving model-based testing methodology we introduce test design patterns for simpl...

Recently, assertion based verification or property checking has become of great interest to the industry. Property checkers attempt either to prove that a specified property, which stipulates expected design behavior, holds or, if the property does not hold, to generate a counter-example that demonstrates a violation of the property. This is another area where there have been some promising suc...

• General approach for the systematic verification of code generators • Seamless test case derivation (process) based on formal specification (i.e. graph transformation rule) • A method is suggested to create test input data for model and code using automated structural test • Results are suitable for making general assumptions about whether or not the code generator’s behaviour is correct Cont...

Modern Design-For-Test (DFT) practices not only simplify test generation but also make it much easier to diagnose problems uncovered in production test. In fact, many diagnostics steps can be automated enough to enable batch processing of large quantities of fail data captured during product ramp and volume production. Hidden in these fail data is very valuable information about the product des...

A novel FPGA design flow combined with automated hierarchical test pattern generation was developed and experimented on a real FPGA circuit for telecommunication. A hierarchical test generator for digital systems described in VHDL is presented. Both, register-transfer (RT) and gate level descriptions are used. Decision diagrams are exploited as a uniform model for describing systems at both lev...

A transformation-based approach to high-level test synthesis is presented. It utilizes a sequence of design-improvement transformations to generate a register-transfer level design from a VHDL behavioral specification. Selection of transformations is based on a performance-driven optimization strategy as well as a testability analysis algorithm which determines the testability-improvement techn...

Systematic design testing, in which executable models of behaviours are tested using inputs that exercise scenarios, can help reveal flaws in designs before they are implemented in code. In this paper a technique for testing executable forms of UML (Unified Modelling Language) models is described and test adequacy criteria based on UML model elements are proposed. The criteria can be used to de...

The systematic test is an inevitable part of the verification and validation process for software. The most important prerequisite for a thorough software test is the design of relevant test cases, since they determine the kind and scope and hence the quality of the test. The classification-tree method and the graphical editor CTE (classification-tree editor) support the systematic design of bl...