1 2 During regression testing, a modified system is often retested using an existing test suite. Since the size of the test suite 3 may be very large, testers are interested in detecting faults in the modified system as early as possible during this retesting 4 process. Test prioritization attempts to order tests for execution so that the chances of early detection of faults during retest5 ing ...

This paper presents a switch-level test generation system for synchronous sequential circuits in which a new algorithm for switch-level test generation and an existing fault simulator are integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models all aspects of switch-level behavior. The time-frame based algorithm uses asynchronous processing wit...

Brookhaven National Laboratory’s Accelerator Test Facility (ATF) has embarked on a complete upgrade of its decade old computer system. The planned improvements affect every major component: processors (Intel Pentium replaces VAXes), operating system (Linux/Real-Time Linux supplants OpenVMS), and data acquisition equipment (fast Ethernet equipment replaces CAMAC serial highway.) This paper summa...

System chip, system on chip (SOC), system on silicon (SOS), there are many terms and many definitions that have arisen to describe the large chips that are emerging as we move further into the murky depths of the deep submicron era. Almost everyone has their own definition of system chip, which may explain why it is that almost everyone can claim to be designing system chips. However, as they b...

This paper describes an application of boundary scan IEEE Std. 1149.1 at system level. It provides the description of the design and the implementation options of a VME boundary scan controller board prototype and the corresponding software. The prototype was designed to use the Module Test and Maintenance (MTM) bus, existing in the VME 64x backplane, to apply the IEEE 1149.1 test vectors to a ...

In this paper, a test pattern generation system for combinational circuits including test pattern generator, fault simulator, and test set compactor is introduced. The techniques that improve test pattern generation process are used in an implemented test pattern generation system called COM_TEST. The results of COM_TEST on ten circuits are given.

This paper covers the concept, architecture, development and demonstration of a Smart Antenna Software Radio Test System (SASRATS). SASRATS was designed and developed as a functional and flexible system to facilitate the field testing of space-time processing architectures and algorithms. It also facilitates the correlation between theoretical, simulated and measured performance. The SASRATS ar...

The elaboration of the signals provided by the fourstripline Beam Position Monitors (BPM) on the superconducting linac TTF will be accomplished by parallel rf circuits, giving a signal of ~1 V /cm, indipendent of beam current, for both horizontal and vertical beam positions with time response ~1μs. and useful range > ±1 cm The performances with respect to thermal drifts and input dynamics are p...