A Framework for Noise Analysis and Verification of Analog Circuits Rajeev Narayanan, Ph.D. Concordia University, 2012 Analog circuit design and verification face significant challenges due to circuit complexity and short market windows. In particular, the influence of technology parameters on circuits, noise modeling and verification still remain a priority for many applications. Noise could be...

This paper defines a real-time rewriting logic semantics for a significant subset of Ptolemy II discreteevent models. This is a challenging task, since such models combine a synchronous fixed-point semantics with hierarchical structure, explicit time, and a rich expression language. The code generation features of Ptolemy II have been leveraged to automatically synthesize a Real-Time Maude veri...

since gait is the mixture of many complex movements, each individual can define with a unique footpressure image that can be used as a reliable biometric scale for human verification. foot pressure colorimages of center for biometrics and security research (cbsr) dataset from 45 men and five womenwere used in this study. owing to the properties of this dataset, an index of foot pressure in addi...

Formal verification of time-dependent properties is crucial in the development of real-time reactive systems for safety-critical applications. Systems modeled in UML (Unified Modeling Language) result in graphic descriptions of the static structure and dynamic behavior of a system and its components. Generating a formal specification from the UML models supports rigorous techniques for validati...

The main obstruction to automatic verification of Finite State Systems is the huge amount of memory required to complete the verification task (state explosion). This motivates research on distributed as well as disk based verification algorithms. In this paper we present a disk based Breadth First Explicit State Space Exploration algorithm as well as an implementation of it within the Murφ ver...

The aim of this chapter is to give an overview of the theoretical foundation and the practical application of logic model checking techniques for the verification of multi-threaded software (rather than hardware) systems. The treatment is focused on the logic model checker SPIN, which was designed for this specific domain of application. SPIN implements an automata-theoretic method of verificat...

We consider the problem of verifying finite state properties of shallow programs; i.e., programs where pointers from program variables to heap-allocated objects are allowed, but where heap-allocated objects may not themselves contain pointers. We prove a number of results relating the complexity of such verification problems to the nature of the finite state machine used to specify the property...

Managing Generic IP verification requires consideration of uncertainties & dynamic changes of standard & specification during project execution. Such scenario requires well defined process which needs to be followed throughout the project execution. A creative approach is required to make sure verification architecture is flexible enough to adapt majority of the run time changes enabling faster...

We discuss the modeling and verification of real-time systems using the SAL model checker. A new modeling framework based on event calendars enables dense timed systems to be described without relying on continuously varying clocks. We present verification techniques that rely on induction and abstraction, and show how these techniques are efficiently supported by the SAL symbolic model-checkin...

This paper presents experiences in using several model checking tools to verify properties of a critical real time embedded system. The tools we tested are Lesar, SMV, Prover Plug In for SCADE and Uppaal. The application is the landing gear control system of a military aircraft, developed by Dassault Aviation. The property to be verified states that the gear must be down in at most 14 seconds. ...