The design of complex Systems-on-Chips implies to take into account communication and timing constraints but also internal memory architecture and mapping for the integration of dedicated hardware accelerator. We present a methodology and a tool that permit the High-Level Synthesis of DSP applications, under both I/O timing and memory constraints. Based on formal models and a generic architectu...

An architecture for integrating the Virtual Path service into the network management architecture of future broadband networks is presented. Complete definitions of Managed Object Classes and behavioral descriptions are given. An experimental platform on top of the XUNET III ATM network provides the proof of concept. The Xunet manager is equipped with the necessary monitoring tools for evaluati...

This paper describes how to realize place-effective synchronous bit-serial constant multiplications, which can be efficiently used for a block of constants (Multiple Constant Multiplication). The architecture combines traditional concepts and new approaches, which leads to the possibility of simultanous fast multiplications of different input values. Fast multiplications are a core for up-to-da...

The InfiniBand(tm) Architecture is a new industry-standard architecture for server I/O and inter-server communication. It was developed by the InfiniBand(sm) Trade Association, a collaboration of over 200 companies including all the major server vendors, to provide the reliability, availability, performance, and scalability needed in server systems. This talk will provide an overview of InfiniB...

In the near future, container ports will no longer be able to expand into the surrounding land and will thus be unable to meet the storage requirements due to the boom in world trade. A solution to this problem is to increase the container throughput of the port by reducing the amount of time necessary to load and unload a ship. This paper presents distributed agent architecture to achieve this...

The PowerPC 601” microprocessor (601) is the first member of a family of processors that support IBM’s PowerPC Architecture”. The 601 Is a general-purpose processor based on a superscalar design point. As with any development effort, the 601 development program had several different, often conflicting, design goals. The most important requirements were support for the PowerPC Architecture, a sh...

This extended abstract defines a class of architectures for pipeline reconfigurable FPGAs by parameterizing a generic model. This class of architectures is sufficiently general to allow exploration of the most important design trade-offs. The parameters include the word size and LUT size, the number of global busses and registers associated with each logic block, and the horizontal interconnect...

Internet application performance over wireless links is disappointing, since wireless impairments adversely affect higher protocol layers. In order to address these problems without global protocol modifications, we examine link layer enhancement schemes. Simulations show that different schemes work best for different applications. We have thus developed a multi-service link layer architecture ...

This report discusses the problem with fault propagation in large scale control systems with object oriented architecture. There seems to be a trade-off between the degree of object encapsulation and the possibility of suppressing propagating error messages – when an individual object detects a fault, it does not in general know how close it is to the real fault, and hence whether it should rep...