This paper propose an efficient algorithm for multipliers modulo . To achieve high speed, the Wallace tree is adopted for the multipliers. The proposed Wallace tree multipliers exhibit much more resular structure than binary Wallace tree cultipliers. Comparison with a previous counterpart shows favorable to our multiplier in both speed and hardware..

‎Assume that $A$ is a Banach algebra‎. ‎We define the‎ ‎$beta-$topology and the $gamma-$topology on the space $QM_{el}(A^{*})$ of all bounded extended left quasi-multipliers of $A^{*}.$‎ ‎We establish further properties of $(QM_{el}(A^{*}),gamma)$ when $A$ is a $C^{*}-$algebra‎. ‎In particular‎, ‎we characterize the $gamma-$dual‎ ‎of $QM_{el}(A^{*})$ and prove that $(QM_{el}(A^{*}),gamma)^{*},$...

In this paper we perform sensitivity analysis for optimization problems with variational inequality constraints (OPVICs). We provide upper estimates for the limiting subdifferential (singular limiting subdifferential) of the value function in terms of the set of normal (abnormal) coderivative (CD) multipliers for OPVICs. For the case of optimization problems with complementarity constraints (OP...

We present a novel approach for computing 2n-bit Montgomery multiplications with n-bit hardware Montgomery multipliers. Smartcards are usually equipped with such hardware Montgomery multipliers; however, due to progresses in factoring algorithms, the recommended bit length of public-key schemes such as RSA is steadily increasing, making the hardware quickly obsolete. Thanks to our doublesize te...

This paper proposes a new method to numerically obtain Floquet multipliers which characterize stability of periodic orbits of ordinary differential equations. For sufficiently smooth periodic orbits, we can compute Floquet multipliers using some standard numerical methods with enough accuracy. However, it has been reported that these methods may produce incorrect results under some conditions. ...

In this paper fast pipelined digit-serial/parallel multipliers are proposed. The conventional digit-serial/parallel multipliers and their pipelined versions are presented. Every structure has been implemented on FPGA and the results are given. These results have been analysed and it is detected that the pipelined ones do not have the throughput improvement expected because of a logic depth incr...

For a Hilbert space H ⊂ L loc (R) of functions on R we obtain a representation theorem for the multipliers M commuting with the shift operator S. This generalizes the classical result for multipliers in L(R) as well as our previous result for multipliers in weighted space L ω (R). Moreover, we obtain a description of the spectrum of S.