This paper introduces a detailed analysis for the operation of the transistor chain in CMOS gates. The chain is modeled by a transistor pair according to the operating conditions of the structure. The system of differential equations for the derived chain model is solved and analytical expressions which accurately describe the temporal evolution of the output voltage, are extracted. For the fir...

|The steady state drift-diiusion model for the ow of electrons and holes in semiconductors is sim-pliied by perturbation techniques. The simpliications amount to assuming zero space charge and low injection. The limiting problems are solved and explicit formulas for the voltage-current characteristics of bipolar devices can be obtained. As examples, the pn-diode, the bipolar transistor and the ...

A novel analytical extension to the PSP transistor model is proposed for static leakage estimation of CMOS circuits considering statistical process variations. Probability equations are inserted directly into the PSP transistor model. Since those equations are completely generic, the proposed methodology is straightforwardly applicable to any technology node. The extended PSP model has been tes...

This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the ...

This study investigates geometrical variability on the sensitivity of the junctionless tunneling field effect transistor (JLTFET) and Heterostructure JLTFET (HJLTFET) performance. We consider the transistor gate dielectric thickness as one of the main variation sources. The impacts of variations on the analog and digital performance of the devices are calculated by using computer aided design (...

This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of ...

Asimple analytic method for transistor oscillator design has been developed. This technique defines explicit expressions for optimum values of feedback elements and load through bipolar transistor z-parameters. Such an approach is useful for practical optimization of a series feedback microwave bipolar oscillator. Microwave oscillator design in general represents a complex problem. Depending on...

A ligamentous, nonlinear, sliding contact, three-dimensional finite element (FE) model of L2-L3 complex was developed to investigate the biomechanical effect of laminectomy with and without facetectomy. The L2-L3 FE model was validated against experimental study under various physiological loadings and found to match well with the experimental data. Four iatrogenic models (unilateral laminectom...

This paper introduces a new approach to pattern dependent static power estimation in logic blocks, which are realized ‘on-the-fly’ in a library-free design environment. A static current model is first developed at the transistor level and then extended to the logic gate level and finally the logic block level. For varying transistors widths and input stimuli, the transistor level model has perf...

In sub-micron technologies MOSFETs are modeled by complex nonlinear equations. These equations include many process parameters, terminal voltages of the transistor and also the transistor geometries; channel width (W) and length (L) parameters. The designers have to choose the most suitable transistor geometries considering the critical parameters, which determine the DC and AC characteristics ...