A known problem in the area of hardware/software codesign is the selection of the proper interface between the different parts of the design. This paper presents a technique which eases the selection by combining different synthesis techniques together with rapid prototyping. Application field of the technique is the design of communication systems where C and VHDL are generated from a specific...

In this paper, we enrich VHDL with new specification constructs intended for hardware verification. Using our extensions, total correctness properties may now be stated whereas only partial correctness can be expressed using the standard VHDL assert statement. All relevant properties can now be specified in such a way that the designer does not need to use formalisms like temporal logics. As th...

∗ This work is supported by National Project and Tsinghua Science Research Foundation. Abstract− In this paper, a visual VHDL integrated design environment VIDE for high level design is presented. In VIDE, there are several graphical and textual mixed design entry tools (VDES) and a graphical objectoriented debugger (VDBG). VDES consists of several diagram editors and a visual text editor, whil...

In this report, we present a top-down VHDL modeling technique which consists of two main modeling levels: speci cation level and functional level. We modeled a RISC Processor (RP) in order to demonstrate the feasibility and e ectiveness of this methodology. All models have been simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results show feasibility...

The ROCCC (Riverside Optimizing Configurable Computing Compiler) is an optimizing C-to-VHDL compiler used to compile routines written in a subset of C to an application-specific circuit on an FPGA. ROCCC incorporates several powerful parallelizing transformations targeted towards code generation for FPGAs and can achieve performance comparable to hand-coded VHDL. We have demonstrated speedups r...

At a high level of abstraction, the VHDL specification of the functionalities that a circuit shall perform is given by defining the behavioral model. The similarity with procedural programming languages suggested to tailor some software analysis techniques to VHDL behavioral description analysis. The aim is to retrieve information on the final circuit from its specifications. The paper presents...

This paper focuses on the integration of the fault injection methodology within the design process of fault-tolerant systems. Due to its wide spectrum of application and hierarchical features, VHDL has been selected as the simulation language to support such an integration. Suitable techniques for injecting faults into VHDL models are identified and depicted. Then, the main features of the MEFI...