A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout o...

This paper describes an approach to VLSI design synthesis using both knowledge-based expert systems and data and control flow analysis. We are concerned with design synthesis as it proceeds from an algorithmic description of a VLSI system to a list of technology-independent registers, operators, data paths, and control signals. This paper discusses the development of the Design Automation Assis...

A VLSI implementation of the symmetric block cipher SAFER K-128 (Secure And Fast Encryption Routine with a Key length of 128 bits) is presented. Possibilities for optimization of the VLSI architecture are explained. The optimizations are based on algorithm specific properties and lead to considerable hardware reduction. The result is a reusable cryptographic VLSI core that allows a data through...

We present a multi-chip neuromorphic system in which an Address Event Representation is used for inter-chip communication. The system comprises an analog VLSI transient imager with adaptive photoreceptors, an analog VLSI motion receiver chip and a prototyping communication infrastructure which allows for programmability of connections between the elements on the two chips. We describe the prope...

The interwire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The upper bounds of the allowable crosstalk for nets, called crosstalk constraints, are usually given in the design speci...

This paper discusses recently introduced strategies in implementing DSP systems using residue replication; in particular we highlight current work underway in the VLSI Research Group, at the University of Windsor, in the area of constructing high throughput DSP systems on silicon. The paper first briefly reviews the theory and mapping techniques, associated with general residue and residue repl...

High-resolution wavefront control for adaptive optics requires accurate sensing of a measure of optical quality. We present two analog very-large-scale-integration (VLSI) image-plane sensors that supply real-time metrics of image and beam quality, for applications in imaging and line-of-sight laser communication. The image metric VLSI sensor quantifies sharpness of the received image in terms o...

Global routing is a crucial step in the design of Very Large-Scale Integration (VLSI) circuits. However, most existing methods are heuristic algorithms, which cannot conjointly optimize subproblems global routing, resulting congestion and overflow. In response to this challenge, an enhanced Deep Reinforcement Learning- (DRL-) based router has been proposed, comprises following effective strateg...

We designed a VLSI chip of FFT multiplier based on simple Cooly Tukey FFT using a floating-point representation with optimal data length based on an experimental error analysis. The VLSI implementation using HITACHI CMOS 0.18μm technology can perform multiplication of 2 to 2 digit hexadecimal numbers 19.7 to 34.3 times (25.7 times in average) faster than software FFT multiplier at an area cost ...

A new very large scale integration (VLSI) algorithmic rule for a 2 N -length discrete hartley transform (DHT) that may be expeditiously enforced on a extremely standard and parallel VLSI design having a regular structure is given. The DHT algorithmic rule may be expeditiously split on many parallel elements that may be dead at the same time. Moreover, the planned algorithmic rule is compatible ...