Multicast communication has increasingly become common and indispensable for Network-on-Chip (NoC). Router is the key unit of NoC, but few of its implementations provide multicast communication directly. In this letter, we design a tree-based multicast router using differentiated subnetwork. Also, we propose a new deadlockfree routing algorithm to overcome the complex deadlock problem on NoC wh...

Chip multiprocessors (CMPs) are gaining momentum in the high-performance computing domain. Networks-on-chip (NoCs) are key components of CMP architectures, in that they have to deal with the communication scalability challenge while meeting tight power, area and latency constraints. 2D mesh topologies are usually preferred by designers of general purpose NoCs. However, manufacturing faults may ...

Chip MultiProcessors (CMPs) have become the primary method of build high-performance microprocessors. Besides speed, major elements such as processing elements and network on chip, allocation and management of on-chip processors are also important factor to achieve high efficiency of future CMPs. In this paper, the authors study a Processor Allocator (PA), especially the issue of its memory uti...

Routing strategies have a key role on communication and performance of the on-chip interconnection networks. Typically, each routing technique can be divided in two parts: output selection and input selection. Several efforts have been done attempting to improve output selection part. But this paper focuses on the improvement of input selection part and investigation of its impact on routers, r...

This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC to...

The communication problem is a challenge issue for Integrated Circuits (ICs), which usually becomes a bottleneck for performance improvement. Three-dimensional integration (3D), as well as network-on-chip (NoC), are two recent design approaches that promise to alleviate the consequences of interconnection degradation. This paper introduces a new methodology for powerefficient application mappin...

Network-on-Chip (NoC) has been introduced to meet the communication challenges for on chip multi-processors and the bandwidth of NoC takes a significant role in area and power consumption of overall system. In order to minimize the bandwidth requirement of NoC, a mapping method is proposed to schedule the tasks of an application onto NoC architecture. More precisely, given the application task ...

A generic analytical performance model of singlechannel wormhole routers is presented using the M/D/1/B queuing theory. Compared with previous work, the flowcontrol feedback mechanism is studied in detail, and a computing method bases on Markov chain for the flowcontrol feedback probability is proposed. Compared with BookSim, a well-known cycle-accurate Network-on-Chip (NoC) simulator, this mod...

Approaching ideal wire latency using a network-on-chip (NoC) is an important practical problem for many-core systems, particularly hundreds-cores. Although other researchers have focused on optimizing large meshes, bypassing or speculating router pipelines, or creating more intricate logarithmic topologies, this paper proposes a balanced combination that trades queue buffers for simplicity. Pre...

As chip complexity keeps increasing in system-on-chip (SoC), the on-chip interconnect has become a critical issue for large-scale chip design. It has been proposed that the packet-switched network exchanging messages between intellectual property (IP) cores is a viable solution for the SoC interconnect problem. The design of the router in such network-on-chip (NoC) architectures is the key to h...