The increasing gap between processor speed and main memory latency has accelerated the development of various innovative architectures from dynamic random access memory(DRAM) vendors. We note that recent DRAM innovations have taken place along three dimensions: reduce access latency, develop new interfaces to achieve higher bandwidth, and add simple logic to the DRAM core for application specii...

introduction: the objective of this study was to examine the influence of sahour meal on exercise performance, and physiological responses to a 10km time-trial (10ktt) at two different times of the day during ramadan. method: three well-trained muslim runners participated (age, 25±0.8years; maximal oxygen uptake, 54.87±3.45 ml.kg-1.min-1; body weight, 52.4±1.99 kg; height, 162.7±3.55 cm).  subj...

Die-stacked DRAM caches represent an emerging technology that offers a new level of cache between SRAM caches and main memory. As compared to SRAM, DRAM caches offer high capacity and bandwidth but incur high access latency costs. Therefore, DRAM caches face new design considerations that include the placement and granularity of tag storage in either DRAM or SRAM. The associativity of the cache...

x latency DTC in two cycles. In contrast, state-of-the-art DRAM cache always reads the tags from DRAM cache that incurs high tag lookup latencies of up to 41 cycles. In summary, high DRAM cache hit latencies, increased inter-core interference, increased inter-core cache eviction, and the large application footprint of complex applications necessitates efficient policies in order to satisfy the ...

This paper summarizes the idea of Tiered-Latency DRAM, which was published in HPCA 2013 [37]. The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical problem in modern memory systems [55]. To this end, TL-DRAM introduces heterogeneity into the design of a DRAM subarray by segmenting the bitlines, thereby creating a low-latency, low-energy, low-capacity portion in the suba...

Phase change memory (PCM) is a promising alternative to DRAM, though its high latency and energy costs prohibit its adoption as a drop-in DRAM replacement. Hybrid memory systems comprising DRAM and PCM attempt to achieve the low access latencies of DRAM at the large capacities of PCM. However, known solutions neglect to assess the utility of data placed in DRAM, and hence fail to achieve high p...

Deep Neural Networks (DNNs) have transformed the field of machine learning (ML) and are widely deployed in many applications involving image, video, speech natural language processing. The increasing compute demands DNNs been addressed through Graphics Processing Units (GPUs) specialized accelerators. However, as model sizes grow, these von Neumann architectures require very high off-chip memor...

A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and >...

This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM thirdgeneration embedded dynamic random-access memory (DRAM) for the IBM Blue Logic 0.11m application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamenta...

A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a high performance microprocessor will typically send more accesses than the DRAM can handle due to the long cycle time of the embedded DRAM, especially in applications with significant memory requirements. A multi-bank...