A design platform for a zero drive load logic inverter consisting of p-channel Si nanowire based transistors, which controlled their operating mode through an implantation into a gate dielectric layer was demonstrated. As a result, a nanowire based class D inverter having a 4.6 gain value at V(DD) of -20 V was successfully fabricated on a substrate.

This paper proposes a single-phase five-level inverter with a modified pulse width-modulated (PWM)control scheme. The modified pulse width-modulation technique is developed to reduce switching loss.Also, the proposed multilevel inverter can reduce the requirement of power switches compared to aconventional cascaded multilevel inverter. The modes of operation, control signals, and operatingprinc...

In this paper we present a 2 input analog Current-Starved Pseudo-Floating Gate (CSPFG) inverter with capacitive feedback. The analog CSPFG inverter suppresses low frequencies due to the active, local feedback. This inverter can be used in designing filters where a narrow band pass or reject is the main goal. Typical applications are detection of high frequency components in sensor signals, i.e....

A six-level inverter system for an open-end winding induction motor drive is presented in this paper. Multilevel inversion is achieved by feeding an open-end winding induction motor with a 3-level inverter from one end and a 2-level inverter from the other end of the motor. The 3level inverter used in the proposed drive, is realized by cascading two 2-level inverters. The combined inverter syst...

The Class DE inverter offers high-efficiency power conversion under high operating frequency (megahertz order) with low switching noises and low switch voltage stress. It has been applied to dc/dc converters as high-density power sources. Conventional converters with the Class DE inverter are controlled by varying the operating frequency, the switch duty ratio or the phase difference with two i...

This research deals w ith simulation and experimentation of closed loop controlled class-D inverter fed induction heater system. This converter has reduced switching losses, stress and increased power density. The inverter system is designed and the simulation is done using Matlab. The results of simulation and experimentation are presented. The induction heater system uses embedded controller ...

This paper proposes fluorescent electronic ballast with high power factor and low line input current harmonics. The system performance can be improved by a charged pump circuit. Details of design and circuit operation are described. The proposed electronic ballast is modified from single stage half bridge class D electronic ballast by adding capacitor parallel with each power switch and setting...

Four di erent CMOS inverter delay models are derived and compared. It is shown that inverter delay can be estimated with fair accuracy over a wide range of input rise times and loads as the sum of two terms, one proportional to the input rise time, and one proportional to the capacitive load. Methods for estimating device capacitance from HSPICE parameters are presented, as well as means of inc...

single phase diode clamped multilevel inverter Department of.This paper presents a single phase multilevel inverter for using as a voltage harmonic source. First, a single phase multilevel inverter system is presented and.The structure of the multilevel inverter using cascaded-inverters with separated dc. single phase multilevel inverter 5 Single-phase configuration of an m-level cascaded inver...