This paper presents a framework for high-level exploration and RTL design of an optimized Network-on-Chip (NoC) architecture for 3D chips. The RTL is derived from the high-level exploration methodology in a semi-automated way. FPGA implementation figures are given for various implementation parameters of the Network Interface Element, demonstrating the performance/area trade-off of 3D NoC archi...

Future integrated circuits that contain more than one billion transistors will allow much more complex designs than possible today. Unfortunately, there will be problems with clock distribution and on-chip communication delays. One approach to address these problems is to make a Network on Chip (NoC), that handles communication over the chip. Research in the area is being done at KTH, and a sim...

NoC(Network-on-Chip) has been proposed as a new solution to deal with the global communication problem of complex SoC(System-on-Chip). However, there are many difficulties in testing and verification for NoC. We propose novel test architectures for 2D-Mesh topology NoC to improve the parallelism of tranferring test packets. The testing efficiencies of different structures are evaluated under a ...

With the rapid shrinking of technology and growing integration capacity, the probability of failures in Networks-on-Chip (NoCs) increases and thus, fault tolerance is essential. Moreover, the unpredictable locations of these failures may influence the regularity of the underlying topology, and a regular 2D mesh is likely to become irregular. Thus, for these failure-prone networks, a viable rout...

This paper presents design trade-off and performance impacts of the amount of pipeline phase of control path signals in a wormhole-switched network-on-chip (NoC). The numbers of the pipeline phase of the control path vary between twoand one-cycle pipeline phase. The control paths consist of the routing request paths for output selection and the arbitration paths for input selection. Data commun...

The smart electronic homes evolution is strongly related to the System-on-Chip (SoC) development. This, in turn, requires an efficient intercommunication between its Intellectuals Proprieties (IPs). Network-on-Chip (NoC) represents the suitable solution. This paper presents a design and implementation of MIC@R NoC architecture performed with non-uniform traffics. This architecture offers lowest...

The Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is the most efficient solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents a GALS and generic NoC architecture based on a configurable router. This router integrates a sophisticated dynamic arbiter, the wormhole routing technique and can be configured in a ...

With the increasing complexity of Multi-Core System-on-Chip (MCSoC) and its communications requirement, Network-on-Chip (NoC) has emerged as a solution of nonscalable shared bus schemes currently used in MCSoC implementation. Recently, a new NoC structure based on WKrecursive network was analyzed and compared to 2D Mesh structure based on several performance metrics such as packet losses, throu...

The thermal challenge of 3D Network-on-Chip (NoC) is severer than 2D NoC. To ensure thermal safety and avoid huge performance back-off from temperature constraint, Runtime Thermal Management (RTM) is required. However the regulation of temperature requires throttling of the nearoverheated router, which makes the topology become NonStationary Irregular Mesh (NSI-mesh). To successfully deliver pa...

The sharply increased complexity of multi-core systems has motivated the architecture of Networks-on-Chip (NoC) to evolve from 2D to 3D. With the objective of optimizing 3D NoC system for specific applications, a new mapping scheme with the goal of reducing signal TSVs and peak temperature is proposed in this paper. The interlayer communication is optimized, which facilitates reduction of signa...