WiMAX (Worldwide Interoperability for Microwave Access) is the emerging wireless technology standard of the near future, which enables high speed packet data access. To anticipate the future demands on WiMAX technology, we proposed an ADPLL (all-digital phase locked loop) solution for the WiMAX system. The developed ADPLL system has targeted frequencies from 2.3 GHz to 2.7 GHz and from 3.3 GHz ...

This paper present an all-digital phaselocked loop (ADPLL)-based frequency synthesizer for Wi-MAX applications implemented in 40-nm CMOS. Via frequency planning and design of multiple capacitor-banks in a digitally-controlled oscillator (DCO), the ADPLL covers dual bands of 2.3–2.7 GHz and 3.3–3.8 GHz, while achieving a fine frequency resolution of25Hz. The time-to-digital converter (TDC) achie...

This paper presents a new quantization noise suppression method for a time-to-digital converter (TDC) and proposes an all-digital phase-locked loop (ADPLL) architecture using only standard cell logic gates. Using a new multiple input multiple output (MIMO) quantization noise suppression method provides an order of √ 2N improvement in TDC resolution with N parallel TDC channels. Suppressed noise...

The cores of the ADPLL-based frequency synthesizer are digital controlled oscillator (DCO) and phase frequency detector (PFD). A modified digitally controlled delay element (DCDE) with characteristics of its monotonicity and insensitivity to PVT variations is presented for the DCO design. We also proposed a new PFD architecture that can finish phase and frequency comparison and adjustment in on...

This paper presents the design rationale and measured results of a low power, low jitter, PVT-stable FBAR-based RF synthesizer implemented in 0.13μm CMOS. A digitally controlled FBAR oscillator, tuned with a switched-capacitor array, provides 5800ppm of frequency tuning, sufficient to cover a wide range of manufacturing and temperature variations of an FBAR. An all-digital phase-locked loop (AD...

In this paper, a new RF/Microwave source is presented. This source is able to generate a Continuous Waveform (CW) signal as well as a modulated signal like GFSK for Bluetooth and GMSK for GSM. The RF source presented here is based on a direct modulation All-Digital Phase-Locked-Loop (ADPLL) architecture that was originally designed for a Bluetooth transmitter in the 2.4GHz in industry, science,...

The mobile communication is often interfered by any type of noises. The all digital phase-locked loop (ADPLL) system has been successfully used for decades in order to track the carrier phase of a frequency modulation (FM) signal. In this paper, we combine the ADPLL and the all-digital amplitude-locked loop (ADALL) system structure for modulation signals of the separation co-channel transmissio...

A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL) designed with a uni...

This work presents an interpolated flying-adder(FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle jitter and root-mean-square (RMS) jitter performance. A multiphase all-digital phase-locked loop (ADPLL) provides steady reference signals for th...

A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6m CMOS process. Test...