This article presents a new clock-less analog-to-digital converter (ADC) based on a full analog signal processing. The main innovative feature of the proposed ADC is that, for a sampled input signal, a cascade of identical stages may operate without timing signal (clock) with its analog processing independent of the output digital signal’s generation. Clock-less converters are used in the medic...

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented, designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit ...

A multibit analog-to-digital converter can achieve high resolution with a lower order modulator and lower oversampling ratio than a single-bit design, but it requires a multibit internal flash analog-to-digital converter rather than a simple comparator. In an implementation with a fully differential analog front end, the flash analog-to-digital converter must quantize a differential voltage rel...

2.6. Hardware Requirements 2.2.1. Sample-and-hold 2.2.2. Analog-to-digital conversion 2.2.3. ADC resolution and error sources Sampling Rates and Timing Quantisation Errors Signal Overflow 2.5.

A novel approach for direct analog-to-residue conversion is presented in this chap/er using the most popular sigma-della analog-to-digital converter. This converter provides high resolulion. high conversion speed and a low cost for implementation. The non-positional nature (~f RNS makes it suitable for fault-toleranl architectures. The error detection and correction properties (?f Redundant Res...

A new Successive-Approximation ADC (Analog-toDigital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 μm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consum...

This paper presents 10-bit, 1.5 MS/s, 2.5V, Low Power Pipeline analog to digital converter using capacitor coupling techniques. A capacitance coupling foldedcascode amplifier effectively saves the power consumption of gain stages of ADC in a 0.25 μm CMOS technology. The ADC also achieves Low power Consumption by the sharing an op-amp between two successive pipeline stage further reduction of po...

A lthough real world signals are analog, it is often desirable to convert them into the digital domain .using an analog to digital converter (ADC). Motivating designers to apply this conversion is the efficient transmission and storage of digital signals. Digital representation of an audio signal, for example, allows CD players to achieve virtually error free storage using optical disks [l]. In...

A flexible, reconfigurable receiver architecture that extends the direct conversion architecture is presented. The receiver structure is based on high dynamic range/lowpower Σ∆ analog-to-digital converters (ADC) and digital signal processing functions implemented locally on the radio frequency integrated circuit (RFIC). This relaxes requirements for the analog part of the receiver and enables c...

The presented work deals with analysis of non-ideal effect of pipelined analog-to-digital converter (ADC) such as random capacitor mismatch, comparator offset and finite op-amp gain. These factors arise during a conversion in the pipelined ADC when using CMOS technology and switched-capacitors (SC) technique. The pipelined ADC was simulated in MATLAB-Simulink simulation environment. Key-Words: ...