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The complexity of Application Specific Integrated Circuits (ASICs) is continuously increasing. Consequently chip-design becomes more and more challenging. To handle this complexity for a fast ASIC development, the existing design process has to become more efficient. To achieve this, we used an approach based on a multi-agent simulation. A mutli-agent system is an intuitive way to represent a t...

Firms are increasingly embracing integrated Web-based or e-supply chains because such chains are believed to enhance efficiency and competitiveness. The e-supply chain movement has received a boost from a variety of off-the-shelf supply chain software solutions that have appeared on the market. However, in the excitement about these software solutions, it is often overlooked that creation and i...

Applied research on growth and innovation seems to suggest that successful innovations do not significantly enhance firm growth. This paper tests the hypothesis that the level of observation at which applied research is typically conducted hampers identification of a significant association between innovation and sales growth rates. Exploiting a unique data set, we find that product innovations...

− There’re mainly two different situations for testing PLD (Programmable Logic Device) devices. One is testing of blank chips that haven’t been programmed; the other is testing of ASIC (Application Specific Integrated Circuit) devices that have been programmed. This paper presents a test method for programmed ASIC devices, including auto test and ATPG (Auto Test Pattern Generation) method for b...

An alternative approach for evaluating the efficiency of integrated circuit (IC) design firms is presented in this paper. We took into account the differences between technology groups, containing one or more design firms, and input and output factors to prevent influences of scale (e.g., firm size). Specifically, we employed a directional distance function approach to data envelopment analysis...

For at least last 30 years microelectronics has been evolving rapidly tracking almost without a single deviation Moore’s Law [3]. Such spectacular progress has been driven by the development of better technologies using constantly improved, but also more expensive, manufacturing equipment. Design and test have followed, struggling with technology-enabled performance opportunities and technology...

This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for GSM/GPRS/EDGE, in order to reduce power and die area as desired for cellular applications. A 2.5G multimode architecture is implemented in 0.13μm CMOS technology occupying 1.0mm and dissipating only 1.3mW in fastest EDGE data transmission mode.

Differential Power Analysis (DPA) is a powerful technique for revealing secret data of cryptographic algorithms such as DES, AES and RSA implemented on a specific platform. In recent years, Correlation Power Analysis (CPA) allowed to better formalize the differential approaches of DPA with the use of a power model. We propose here two methods in order to optimize the power model for the targete...