This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which al...

This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshakecomponent-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an areaefficient architecture of an FPGA that is suitable for handshake-componentbased asynchronous circuit. Moreover, the Four-Phase Dual-Rail en...

Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read ope...

Although the benefits of asynchronous design style are undeniable, this style is still a road that designers rather avoid. There are, however, serious advantages of this digital design concept that are making it favourable for many applications. Asynchronous circuits need no clock generation and distribution (Sparso, 2006; Martin & Nystrom 2006), which leaves the problems related to clock skew ...

The (non-initialized, non-deterministic) asynchronous systems (in the input-output sense) are multi-valued functions from m-dimensional signals to sets of n-dimensional signals, the concept being inspired by the modeling of the asynchronous circuits. Our purpose is to state the problem of the their stability.

Field Programmable Gate Arrays (FPGAs) are used to embed a circuit designed by users instantly. Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. Howe...

A weak asynchronous system is a trace monoid with a partial action on a set. A polygonal morphism between weak asynchronous systems commutes with the actions and preserves the independence of events. We prove that the category of weak asynchronous systems and polygonal mor-phisms has all limits and colimits.

Article history: Received 1 July 2015 Received in revised form 7 July 2015 Accepted 8 July 2015 Available online xxxx