ATPG vectors for a combinational circuit exhibit correlations among the bits of a test vector. We propose a BIST/decompressor circuit design methodology using spectral methods which utilizes the correlation information. This circuit serves dual purposes. It generates BIST vectors that are similar to the ATPG vectors with higher test coverage as compared to random and weighted random vectors. Th...

Due to ever increasing design sizes, more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently, SAT-based approaches for test pattern generation have been shown to be very efficient even on large industrial circuits. But these SAT-based techniques are not always superior to classical ATPG approaches. An integration of SAT-based engines into the classical ATPG flow c...

Circuit partitioned approaches to ATPG have been developed and used over the last two decades, depending on the ratio between state-of-the-art in ATPG and circuit sizes. A practical form consists of coarse-grain, cone-oriented partitioning of the circuit. We investigated the problems introduced by practical ATPG constraints: keeping tests (3-state) bus-conflict free, and complying to external r...

Delay fault testing has proven to be a significant part of modern manufacturing testing. It has also become a source of overtesting due to detection of functionally untestable faults by invalid transitions that would not occur during functional operation of the chip. There has been previous work in the field that identifies these faults allowing them to be removed from active fault lists from A...

The paper describes an environment for an Internet-based co-operation in the field of design and test of digital systems. A VLSI design flow is combined with an Internetbased hierarchical automated test pattern generation (ATPG). A novel hierarchical ATPG driven by testability measures is presented. Both, the register-transfer (RT) and the gate level descriptions are used, and decision diagrams...

Modern technologies have enabled the semiconductor industry to enter a new era of integrated-circuit manufacturing. Modern ICs are not only smaller and signi cantly more high-performing than they used to be only a few years ago; they are also considerably more energy-e cient thanks to the use of new materials with convenient electric properties. However, the use of new materials is also making ...

We present an efficient register-transfer level automatic test pattern generation (ATPG) algorithm. First, our ATPG generates a series of sequential justification and propagation paths for each RTL primitive via a deterministic branch-and-bound search process, called a test environment. Then the precomputed test vectors for the RTL primitives are plugged into the generated test environments to ...

The aim with this paper is to design a high efficient sequential ATPG on single stack-at fault model. A new approach for sequential circuit test generation is proposed in this paper. With combining the advantage of logic simulation based ATPG and fault simulation based ATPG, higher fault coverage and shorter test sequential length are achieved for benchmark circuit instead of pure logic or faul...

SAT-based ATPG has proven to be a beneficial complement to traditional ATPG techniques. The generation of a CNF-representation is a vital issue in SAT-based test pattern generation. Firstly, the generation of the problem instances for SAT-based ATPG requires a significant portion of the overall runtime. Secondly, the performance of the SAT solver strongly depends on the properties of the result...

Most published ATPG methods cannot handle three-state primitives, generate too large test sets, or require excessive CPU time. An eecient ATPG system was introduced in 1]]2], which can handle non-Boolean prim-itives, generates compact test sets, within aaordable CPU time. In this paper, the system is extended to handle pulled and wired buses, in addition to pure three-state buses. These bus typ...