In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer insertion issues in structured ASIC design style. We design the layout for two dedicated buffers and ex...

In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer insertion issues in structured ASIC design style. We design the layout for two dedicated buffers and ex...

In this paper we have analyzed the advantages of using dynamic circuits over static circuits with result oriented example for NAND operation. The different aspects covered under this discussion include power, speed, area, input Capacitance and timing delays calculation. We have also covered the problem of increase in dynamic power dissipation at the dynamic and the output node in dynamic circui...

Through technology development, VLSI fabrication is becoming smaller in size which causes much sensitivity of VLSI circuit to noise effects especially soft error. In this paper, we present a method to mitigate soft error in combinational logic gates based on 65 nm technology that is able to reduce the possibility of noise propagation in combinational logic gate. We evaluate our result based on ...

The dataset of physical properties for the proposed CIGS solar cell with Cd-free AlGaAs buffer layer has been depicted in this data article. The cell performance outcome due to different AlGaAs buffer layer band gap is reported along with optimum solar cell performance parameters for instance, open circuit voltage [Formula: see text], short circuit current density ([Formula: see text], fill fac...

A very simple circuit design of a bidirectional input/output(I/O) buffer is proposed for mixed voltage interface applications. By a floating N-well circuit technique two series PMOS transistors are used as an active pull-up driver. Such a structure provides a simple circuit that requires only a single terminal pad, a single power supply, and is free of DC leakage current. Mixed voltage interfac...

This paper describes a CMOS analogy voltage supper buffer designed to have extremely low static current Consumption as well as high current drive capability. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation. The name of applied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speed buffer with the redu...

In credit-based flow control for ATM networks, switch buffer space is first allocated to each virtual circuit (VC) and then credit control is applied to the VC to prevent possible buffer overflow. Adaptive buffer allocation improves sharing by allowing dynamic allocation of buffer space to multiple VCs sharing the same buffer pool. This paper gives an overview of credit flow control and present...

As VLSI technology enters the nanoscale regime, a great amount of efforts have been made to reduce interconnect delay. Among them, buffer insertion stands out as an effective technique for timing optimization. A dramatic rise in on-chip buffer density has been witnessed. For example, in two recent IBM ASIC designs, 25% gates are buffers. In this thesis, three buffer insertion algorithms are pre...