نتایج جستجو برای: bus scheduling

تعداد نتایج: 91344  

1995
Ching-Chih Han Kang G. Shin

There has been an increasing need of timely and predictable communication services for embedded real-time systems in automated factories and industrial process controls. Work has been done on real-time communication with deadline guarantees in point-to-point, token bus/token ring/FDDI, and DQDB (Distributed Queue Dual Bus) networks. However, due to the random access nature of the CSMA/CD type m...

2008
Dumitru Potop-Butucaru Yves Sorel

We consider the problem of minimizing bus usage for static real-time scheduling of hierarchical dataflow specifications involving conditional execution. Statically scheduling conditional communications over an asynchronous broadcast bus involves the sending of the activation conditions themselves, which allow all processors to know which messages they must throw away or use. As the communicatio...

2012
N. A. RAHIM

There are various methods applied for indicating the most sensitive bus for any corrective and preventive actions like power scheduling at generation site and shunt element placement such as capacitor bank and FACTS devices at load site. The methods can be sensitivity analysis, optimization method, stability index based ranking and lastly the method that is rarely applied, termed as power traci...

2003
Traian Pop Petru Eles Zebo Peng

This paper deals with specific issues related to the design of distributed embedded systems implemented with mixed, event-triggered and time-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases. Such systems are emerging as a new standard for automotive applications. We have developed a holistic timing analysis and scheduling approach for this c...

2015
P. Ávila F. Irarragorri R. Caballero

The urban transport planning process has four basic activities: network design, timetable construction, vehicle scheduling and crew scheduling. In this work we focus on the urban bus timetable construction problem which has two sub-activities: bus frequency calculation and bus departures setting. Typically, these sub-activities are done sequentially, which has some drawbacks: to overcome these ...

1999
Mohammad Ali Livani Jörg Kaiser

As a common resource, the CAN bus has to be shared by all computing nodes. Access to the bus has to be scheduled in a way that distributed computations meet their deadlines in spite of competition for the communication medium. The paper presents an evaluation of a resource scheduling scheme for CAN, which is based on time-slot reservation and dynamic priorities. The processing overhead as well ...

Journal: :Trans. HiPEAC 2009
Khaled Z. Ibrahim Smaïl Niar

Execution time for realtime processes running on multiprocessor systemon-chip platform varies due to the contention on the bus. Considering the worst case execution cycles necessitates over-clocking the system to meet the realtime deadlines, which has a negative impact on the system power requirements. For periodic applications coscheduled on multiprocessor with shared bus, the cycles needed by...

1999
Henrik Lönn Jakob Axelsson

This paper compares different scheduling policies applied to distributed systems intended for automotive real-time control applications. We describe the characteristics of systems using fixed priority (FP) and static cyclic (SC) scheduling of processors and bus communication, with combinations ranging from FP bus-FP processors to SC bus-SC processors. FP bus is represented by the Controller Are...

2003
K. Keutzer S. Malik A. R. Newton

This paper presents a new hardware-software co-design methodology for resource constrained SoC realized in a deep submicron process (DSM). The methodology is useful for multimedia applications optimized for latency. The approach addresses layout and hardware aspects relevant to system design: it considers the dependency of task communication speed on interconnect parasitic, as well as the possi...

2004
Zili Shao Qingfeng Zhuge Meilin Liu Bin Xiao Edwin Hsing-Mean Sha

This paper develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from ...

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