We explore a method for automatically recompiling quantum circuit A into target B, with the goal that both circuits have same action on specific input i.e. B|in> = A|in>. This is of particular relevance to hybrid, NISQ-era algorithms dynamical simulation or eigensolving. The user initially specifies B as blank template: layout parameterised unitary gates configured identity. compilation then pr...

Many optimisation problems in circuit design, in the following also refereed to as VLSI CAD, consist of mutually dependent sub-problems, where the resulting solutions must satisfy several requirements. Recently, a new model for Multi-Objective Optimisation (MOO) for applications in Evolutionary Algorithms (EAs) has been proposed. The search space is partitioned into socalled Satisfiability Clas...

This paper presents a self-actuating biosensor based on the piezoelectric cantilever optimized by Taguchi method for the label-free detection of specific biomoleculars. Until now, even though the optimisation of the cantilever-based biosensors have been performed by changing dimensions one by one, few researches have performed the geometric optimisation considering the overall configuration of ...

SPICE is a widely used tool for simulation of analog circuits. Accurate models of devices are crucial for obtaining realistic results from the simulation. Although SPICE provides circuit designers with built-in models for most widely used devices many devices still must be modelled with subcircuit models in order to achieve sufficient accuracy. The hardest part of creating a SPICE model for a p...

Circuit sizing problem in application specific analog integrated circuit design is in most cases limited to setting MOSFET channel widths and lengths. It is usually performed by hand by an experienced human designer. As the circuit sizing is an optimization process by its nature, optimization methods could be used. They always lead to one of the minima of the cost function while eventual other ...

This paper presents an algorithm for efficient distribution of completion detection blocks in a dualrail self-timed circuit to ensure correct computation of the completion signal. Layer-wise optimisation technique is used with the width of layers selected so as to satisfy timing constrains and use the least possible number of completion detection blocks.