In this paper, we study two diverse problems from a random matrix perspective. The first one is the problem of binary testing (or object/entity identification) that arises in applications such as active learning, fault diagnosis and computer vision, and the second is the problem of zero or bounded skew clock tree construction which arises in applications such as VLSI circuit design and network ...

We introduce a new approach for optimizing clock tree, especially for high-speed circuits. Our approach provides a useful guideline to a designer; by user-speciied parameters, design favors will be satissed. Three of these tradeoos will be provided in this chapter. 1) First, to provide a \good" tradeoo between skew and wirelength, a new clock tree routing scheme is proposed. The technique is ba...

We study the problem of multi-stage zero skew clock tree construction for minimizing clock phase delay and wirelength. In existing approaches clock bu ers are inserted only after clock tree is constructed. The novelty of this paper lies in simultaneously perform clock tree routing and bu er insertion. We propose a clustering-based algorithm which uses shortest delay as the cost function. We sho...

This paper presents new single-layer, i.e., planarembeddable, clock tree constructions with exact zero skew under either the linear or the Elmore delay model. Our method, called Planar-DME, consists of two parts. The first algorithm, called Linear-Planar-DME, guarantees an optimal planar zero-skew clock tree (ZST) under the linear delay model. The second algorithm, called Elmore-Planar-DME, use...

This paper presents new single-layer, i.e., planar-embeddable, clock tree constructions with exact zero skew under either the linear or the Elmore delay model. Our method, called Planar-DME, consists of two parts. The rst algorithm, called Linear-Planar-DME, guarantees an optimal planar zero-skew clock tree (ZST) under the linear delay model. The second algorithm, called ElmorePlanar-DME, uses ...

Multi-Chip Modules (MCM's) provide a medium for integration of several bare dies on a multi-layer substrate. MCM technology has gained popularity in recent years with the promise of orders of magnitude reduction in inter-chip delay and power dissipation over single chip packaging [2]. By virtue of a faster interconnect MCM's aim at alleviating, to a large extent, the bottleneck o ered by conven...

In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we rst present the Deferred-Merge Embedding (DME) algorithm, which embeds ...

Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low power clock tree by distributing the clock signal at a lower voltage, and translating it to a higher voltage at the utilization points. Two low power schemes are used: reduced swing and multiple supply voltages. We ana...

As VLSI technology advances into nanometer dimensions, clock routing becomes a limiting factor in determining chip performance. To deal with the challenge, X-architecture has been proposed and widely applied in routing field because it contributes more improvements in terms of the clock delay, wirelength, and power consumption than general Manhattan-architecture. This work proposes an X-archite...

We present Badger, a new fast and provably secure MAC based on universal hashing. In the construction, a modified tree hash that is more efficient than standard tree hash is used and its security is being proven. Furthermore, in order to derive the core hash function of the tree, we use a novel technique for reducing ∆-universal function families to universal families. The resulting MAC is very...