This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator an...

Circuit delays in MOS integrated circuits often need to be reduced to obtain faster response times, with a minimal area penalty. A typical MOS digital integrated circuit consists of multiple stages of combinational logic blocks that lie between latches, clocked by system clock signals. Delay reduction must ensure that the worst-case delay of the combinational blocks is such that valid signals r...

Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. GPP Logic Circuit Synthesizer (GPPLCS) is a combinational logic circuit learning system based on GPP. The GPPLCS comprises a MultiLogic-Unit Processor (MLP) which is a hardware processor built on a Field Programmable Gate Array (FPGA). The MLP is designed to speed up the evaluation of genetic parallel programs that repr...

A novel synthesis method for self-timed realization of arbitrary combinational logic functions is presented in this paper. The cost of self-timed implementation of a large number of conventional combinatorial benchmarks is provided. A new self-timed system configuration is also proposed in support of the synthesis heuristic that generally favors weakly indicating realizations of combinational l...

We present a new model for representing timing information for functions in High-Level Synthesis (HLS). We identify shortcomings of the conventional timing model, which is a very simple model derived from the combinational logic model, and show that our new model overcomes many of these defects. In particular, we are able to provide a unified timing model that describes hierarchical combination...

---------------------------------------------------ABSTRACT------------------------------------------------------Advanced Encryption Standard (AES) block cipher system is widely used in cryptographic applications. The main core of AES block cipher is the substitution table or SBox. This S-box is used to provide confusion capability for AES. In addition, to strengthen the S-Box against algebraic...

Combinational Circuits are defined as the circuit whose output depends on present inputs only and are memory less.Thesecircuits are generally acyclic (feed-forward) but cyclic circuits can be combinational where cycles sometimes occur in designs synthesized from high-level descriptions. Feedbackinsuch cases is carefully contrived when functional units are connected in a cyclic topology. Deliber...

With the growth in size and complexity of integrated circuits, test generation for them is becoming increasingly difficult, so it is important to find new and effective digital integrated circuit test generation algorithm. In order to improve the quality of combinational test generation, a combinational circuits test generation algorithm based three-valued neural networks [1] is proposed in thi...