We investigate two scalar coprocessors for accelerating the ITU-T G723.1 and G729A speech coders. Architecture space exploration indicates up to 72% reduction in the total number of instructions executed through the introduction of custom instructions and small changes to the C reference code. The accelerators are designed to be attached to a configurable embedded RISC CPU where they make use o...

We investigate two scalar coprocessors for accelerating the ITU-T G723.1 and G729A speech coders. Architecture space exploration indicates up to 72% reduction in the total number of instructions executed through the introduction of custom instructions and small changes to the C reference code. The accelerators are designed to be attached to a configurable embedded RISC CPU where they make use o...

In recent years, in various sectors of our society, there have been nationalist stirrings which were crystallized and articulated by the late Claro M. Recto, There were jealous demands for the recognition of Philippine sovereignty on the Bases question. There were appeals for the correction of the iniquitous economic relations between the Philippines and the United States. For a time, Filipino ...

Reducing processor-memory speed gap is one of the major challenges computer architects face today. Efficient use of CPU registers reduces the number of memory accesses. However, registers do incur extra overhead of Load/Store, register allocation and saving of register context across procedure calls. Caches however do not have any such overheads and cache technology has matured to the extent th...

It is essential to understand the consumption pattern of food and how it changes over time to formulate sound economic policies as well as marketing and pricing strategies. In this study, we estimate the Quadratic Almost Ideal Demand System with six rounds of the Family Income Expenditure Survey exploiting the conditional linearity of the demand system. We find that the Filipino diet has become...

In an Infrastructure as a Service (IaaS), the amount of resources allocated to a virtual machine (VM) at creation time may be expressed with relative values (relative to the hardware, i.e., a fraction of the capacity of a device) or absolute values (i.e., a performancemetric which is independent from the capacity of the hardware). Surprisingly, disk or network resource allocations are expressed...

ALU stands for arithmetic logic unit. As insinuated by its name, the ALU handles any arithmetic or logic requirements needed by the processor. This includes basic arithmetic operations such as addition, multiplication, and Boolean instructions. The CPU gives the inputs to the ALU through the data buses. The size of the buses can vary greatly, based on the bit of the CPU. Along with the data, an...

We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new mode improves main memory bandwidth, CPU efficiency, cache hits, and cache latency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.

Coherent-cache shared-memory architectures often give disappointing performance which can be alleviated by manual tuning. We describe a new trace analysis tool, clarissa, which helps diagnose problems and pinpoint their causes. Unusually, clarissa works by analysing potential contention, instead of measuring predicted contention by simulating a speciic memory system design. This is important be...

This paper presents a novel technique for cycleaccurate simulation of the Central Processing Unit (CPU) of a modern superscalar processor, the UltraSPARC III Cu processor. The technique is based on adding a module to an existing fetch-decode-execute style of CPU simulator, rather than the traditional method of fully modelling the CPU microarchitecture. It is also suitable for accurate SMP model...